diff mbox series

[v4,143/163] tcg/s390x: Remove support for add2/sub2

Message ID 20250415192515.232910-144-richard.henderson@linaro.org
State New
Headers show
Series tcg: Convert to TCGOutOp structures | expand

Commit Message

Richard Henderson April 15, 2025, 7:24 p.m. UTC 
We have replaced this with support for add/sub carry.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/s390x/tcg-target-con-set.h |  2 --
 tcg/s390x/tcg-target-has.h     |  8 +++---
 tcg/s390x/tcg-target.c.inc     | 50 ----------------------------------
 3 files changed, 4 insertions(+), 56 deletions(-)

Comments

Pierrick Bouvier April 16, 2025, 7:18 p.m. UTC | #1 
On 4/15/25 12:24, Richard Henderson wrote:
> We have replaced this with support for add/sub carry.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   tcg/s390x/tcg-target-con-set.h |  2 --
>   tcg/s390x/tcg-target-has.h     |  8 +++---
>   tcg/s390x/tcg-target.c.inc     | 50 ----------------------------------
>   3 files changed, 4 insertions(+), 56 deletions(-)
> 
> diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
> index 0a991f6d5d..f67fd7898e 100644
> --- a/tcg/s390x/tcg-target-con-set.h
> +++ b/tcg/s390x/tcg-target-con-set.h
> @@ -45,5 +45,3 @@ C_O2_I1(o, m, r)
>   C_O2_I2(o, m, 0, r)
>   C_O2_I2(o, m, r, r)
>   C_O2_I3(o, m, 0, 1, r)
> -C_N1_O1_I4(r, r, 0, 1, ri, r)
> -C_N1_O1_I4(r, r, 0, 1, rUV, r)
> diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h
> index 4a2b71995d..17e61130cd 100644
> --- a/tcg/s390x/tcg-target-has.h
> +++ b/tcg/s390x/tcg-target-has.h
> @@ -29,13 +29,13 @@ extern uint64_t s390_facilities[3];
>       ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1)
>   
>   /* optional instructions */
> -#define TCG_TARGET_HAS_add2_i32       1
> -#define TCG_TARGET_HAS_sub2_i32       1
> +#define TCG_TARGET_HAS_add2_i32       0
> +#define TCG_TARGET_HAS_sub2_i32       0
>   #define TCG_TARGET_HAS_extr_i64_i32   0
>   #define TCG_TARGET_HAS_qemu_st8_i32   0
>   
> -#define TCG_TARGET_HAS_add2_i64       1
> -#define TCG_TARGET_HAS_sub2_i64       1
> +#define TCG_TARGET_HAS_add2_i64       0
> +#define TCG_TARGET_HAS_sub2_i64       0
>   
>   #define TCG_TARGET_HAS_qemu_ldst_i128 1
>   
> diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
> index 36293d0f42..09c7ca5b44 100644
> --- a/tcg/s390x/tcg-target.c.inc
> +++ b/tcg/s390x/tcg-target.c.inc
> @@ -3064,23 +3064,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
>           tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
>           break;
>   
> -    case INDEX_op_add2_i32:
> -        if (const_args[4]) {
> -            tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
> -        } else {
> -            tcg_out_insn(s, RR, ALR, args[0], args[4]);
> -        }
> -        tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
> -        break;
> -    case INDEX_op_sub2_i32:
> -        if (const_args[4]) {
> -            tcg_out_insn(s, RIL, SLFI, args[0], args[4]);
> -        } else {
> -            tcg_out_insn(s, RR, SLR, args[0], args[4]);
> -        }
> -        tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
> -        break;
> -
>       case INDEX_op_br:
>           tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0]));
>           break;
> @@ -3124,31 +3107,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
>           tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
>           break;
>   
> -    case INDEX_op_add2_i64:
> -        if (const_args[4]) {
> -            if ((int64_t)args[4] >= 0) {
> -                tcg_out_insn(s, RIL, ALGFI, args[0], args[4]);
> -            } else {
> -                tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]);
> -            }
> -        } else {
> -            tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
> -        }
> -        tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
> -        break;
> -    case INDEX_op_sub2_i64:
> -        if (const_args[4]) {
> -            if ((int64_t)args[4] >= 0) {
> -                tcg_out_insn(s, RIL, SLGFI, args[0], args[4]);
> -            } else {
> -                tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]);
> -            }
> -        } else {
> -            tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
> -        }
> -        tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
> -        break;
> -
>       case INDEX_op_mb:
>           /* The host memory model is quite strong, we simply need to
>              serialize the instruction stream.  */
> @@ -3643,14 +3601,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
>       case INDEX_op_qemu_st_i128:
>           return C_O0_I3(o, m, r);
>   
> -    case INDEX_op_add2_i32:
> -    case INDEX_op_sub2_i32:
> -        return C_N1_O1_I4(r, r, 0, 1, ri, r);
> -
> -    case INDEX_op_add2_i64:
> -    case INDEX_op_sub2_i64:
> -        return C_N1_O1_I4(r, r, 0, 1, rUV, r);
> -
>       case INDEX_op_st_vec:
>           return C_O0_I2(v, r);
>       case INDEX_op_ld_vec:

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff mbox series

Patch

diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 0a991f6d5d..f67fd7898e 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -45,5 +45,3 @@  C_O2_I1(o, m, r)
 C_O2_I2(o, m, 0, r)
 C_O2_I2(o, m, r, r)
 C_O2_I3(o, m, 0, 1, r)
-C_N1_O1_I4(r, r, 0, 1, ri, r)
-C_N1_O1_I4(r, r, 0, 1, rUV, r)
diff --git a/tcg/s390x/tcg-target-has.h b/tcg/s390x/tcg-target-has.h
index 4a2b71995d..17e61130cd 100644
--- a/tcg/s390x/tcg-target-has.h
+++ b/tcg/s390x/tcg-target-has.h
@@ -29,13 +29,13 @@  extern uint64_t s390_facilities[3];
     ((s390_facilities[FACILITY_##X / 64] >> (63 - FACILITY_##X % 64)) & 1)
 
 /* optional instructions */
-#define TCG_TARGET_HAS_add2_i32       1
-#define TCG_TARGET_HAS_sub2_i32       1
+#define TCG_TARGET_HAS_add2_i32       0
+#define TCG_TARGET_HAS_sub2_i32       0
 #define TCG_TARGET_HAS_extr_i64_i32   0
 #define TCG_TARGET_HAS_qemu_st8_i32   0
 
-#define TCG_TARGET_HAS_add2_i64       1
-#define TCG_TARGET_HAS_sub2_i64       1
+#define TCG_TARGET_HAS_add2_i64       0
+#define TCG_TARGET_HAS_sub2_i64       0
 
 #define TCG_TARGET_HAS_qemu_ldst_i128 1
 
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 36293d0f42..09c7ca5b44 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -3064,23 +3064,6 @@  static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
         tcg_out_st(s, TCG_TYPE_I32, args[0], args[1], args[2]);
         break;
 
-    case INDEX_op_add2_i32:
-        if (const_args[4]) {
-            tcg_out_insn(s, RIL, ALFI, args[0], args[4]);
-        } else {
-            tcg_out_insn(s, RR, ALR, args[0], args[4]);
-        }
-        tcg_out_insn(s, RRE, ALCR, args[1], args[5]);
-        break;
-    case INDEX_op_sub2_i32:
-        if (const_args[4]) {
-            tcg_out_insn(s, RIL, SLFI, args[0], args[4]);
-        } else {
-            tcg_out_insn(s, RR, SLR, args[0], args[4]);
-        }
-        tcg_out_insn(s, RRE, SLBR, args[1], args[5]);
-        break;
-
     case INDEX_op_br:
         tgen_branch(s, S390_CC_ALWAYS, arg_label(args[0]));
         break;
@@ -3124,31 +3107,6 @@  static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type,
         tcg_out_st(s, TCG_TYPE_I64, args[0], args[1], args[2]);
         break;
 
-    case INDEX_op_add2_i64:
-        if (const_args[4]) {
-            if ((int64_t)args[4] >= 0) {
-                tcg_out_insn(s, RIL, ALGFI, args[0], args[4]);
-            } else {
-                tcg_out_insn(s, RIL, SLGFI, args[0], -args[4]);
-            }
-        } else {
-            tcg_out_insn(s, RRE, ALGR, args[0], args[4]);
-        }
-        tcg_out_insn(s, RRE, ALCGR, args[1], args[5]);
-        break;
-    case INDEX_op_sub2_i64:
-        if (const_args[4]) {
-            if ((int64_t)args[4] >= 0) {
-                tcg_out_insn(s, RIL, SLGFI, args[0], args[4]);
-            } else {
-                tcg_out_insn(s, RIL, ALGFI, args[0], -args[4]);
-            }
-        } else {
-            tcg_out_insn(s, RRE, SLGR, args[0], args[4]);
-        }
-        tcg_out_insn(s, RRE, SLBGR, args[1], args[5]);
-        break;
-
     case INDEX_op_mb:
         /* The host memory model is quite strong, we simply need to
            serialize the instruction stream.  */
@@ -3643,14 +3601,6 @@  tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags)
     case INDEX_op_qemu_st_i128:
         return C_O0_I3(o, m, r);
 
-    case INDEX_op_add2_i32:
-    case INDEX_op_sub2_i32:
-        return C_N1_O1_I4(r, r, 0, 1, ri, r);
-
-    case INDEX_op_add2_i64:
-    case INDEX_op_sub2_i64:
-        return C_N1_O1_I4(r, r, 0, 1, rUV, r);
-
     case INDEX_op_st_vec:
         return C_O0_I2(v, r);
     case INDEX_op_ld_vec: