| Message ID | 20250415192515.232910-98-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Convert to TCGOutOp structures | expand |
On 4/15/25 12:24, Richard Henderson wrote: > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> > --- > tcg/tcg.c | 22 +++++++++++++++++++--- > tcg/aarch64/tcg-target.c.inc | 2 -- > tcg/i386/tcg-target.c.inc | 2 -- > tcg/loongarch64/tcg-target.c.inc | 2 -- > tcg/mips/tcg-target.c.inc | 2 -- > tcg/ppc/tcg-target.c.inc | 2 -- > tcg/riscv/tcg-target.c.inc | 2 -- > tcg/s390x/tcg-target.c.inc | 2 -- > tcg/sparc64/tcg-target.c.inc | 2 -- > tcg/tci/tcg-target.c.inc | 2 -- > 10 files changed, 19 insertions(+), 21 deletions(-) > > diff --git a/tcg/tcg.c b/tcg/tcg.c > index e688cd12b7..35f192e483 100644 > --- a/tcg/tcg.c > +++ b/tcg/tcg.c > @@ -1068,6 +1068,23 @@ QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetState, tlb.f[0]) - > < MIN_TLB_MASK_TABLE_OFS); > #endif > > +#if TCG_TARGET_REG_BITS == 64 > +/* > + * We require these functions for slow-path function calls. > + * Adapt them generically for opcode output. > + */ > + > +static void tgen_exts_i32_i64(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) > +{ > + tcg_out_exts_i32_i64(s, a0, a1); > +} > + > +static const TCGOutOpUnary outop_exts_i32_i64 = { > + .base.static_constraint = C_O1_I1(r, r), > + .out_rr = tgen_exts_i32_i64, > +}; > +#endif > + > /* > * Register V as the TCGOutOp for O. > * This verifies that V is of type T, otherwise give a nice compiler error. > @@ -1122,6 +1139,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = { > OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2), > #else > OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), > + OUTOP(INDEX_op_ext_i32_i64, TCGOutOpUnary, outop_exts_i32_i64), > #endif > }; > > @@ -5409,9 +5427,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) > /* emit instruction */ > TCGType type = TCGOP_TYPE(op); > switch (op->opc) { > - case INDEX_op_ext_i32_i64: > - tcg_out_exts_i32_i64(s, new_args[0], new_args[1]); > - break; > case INDEX_op_extu_i32_i64: > tcg_out_extu_i32_i64(s, new_args[0], new_args[1]); > break; > @@ -5474,6 +5489,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) > break; > > case INDEX_op_bswap64: > + case INDEX_op_ext_i32_i64: > assert(TCG_TARGET_REG_BITS == 64); > /* fall through */ > case INDEX_op_ctpop: > diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc > index 00400f6ea7..68f7a1cec2 100644 > --- a/tcg/aarch64/tcg-target.c.inc > +++ b/tcg/aarch64/tcg-target.c.inc > @@ -2710,7 +2710,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > default: > @@ -3177,7 +3176,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_ld32u_i64: > case INDEX_op_ld32s_i64: > case INDEX_op_ld_i64: > - case INDEX_op_ext_i32_i64: > case INDEX_op_extu_i32_i64: > return C_O1_I1(r, r); > > diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc > index 6a5414ab3a..14b912beb7 100644 > --- a/tcg/i386/tcg-target.c.inc > +++ b/tcg/i386/tcg-target.c.inc > @@ -3413,7 +3413,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > default: > @@ -4001,7 +4000,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_extrh_i64_i32: > return C_O1_I1(r, 0); > > - case INDEX_op_ext_i32_i64: > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > return C_O1_I1(r, r); > diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc > index c88db7a0e2..e2dbd08e12 100644 > --- a/tcg/loongarch64/tcg-target.c.inc > +++ b/tcg/loongarch64/tcg-target.c.inc > @@ -1931,7 +1931,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > default: > @@ -2462,7 +2461,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > case INDEX_op_extrh_i64_i32: > - case INDEX_op_ext_i32_i64: > case INDEX_op_ld8s_i32: > case INDEX_op_ld8s_i64: > case INDEX_op_ld8u_i32: > diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc > index 56c58bf82d..e992a468eb 100644 > --- a/tcg/mips/tcg-target.c.inc > +++ b/tcg/mips/tcg-target.c.inc > @@ -2364,7 +2364,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > default: > @@ -2391,7 +2390,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_ld32s_i64: > case INDEX_op_ld32u_i64: > case INDEX_op_ld_i64: > - case INDEX_op_ext_i32_i64: > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > case INDEX_op_extrh_i64_i32: > diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc > index 3d1ffa9130..fea767573c 100644 > --- a/tcg/ppc/tcg-target.c.inc > +++ b/tcg/ppc/tcg-target.c.inc > @@ -3640,7 +3640,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > default: > @@ -4270,7 +4269,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_ld32u_i64: > case INDEX_op_ld32s_i64: > case INDEX_op_ld_i64: > - case INDEX_op_ext_i32_i64: > case INDEX_op_extu_i32_i64: > return C_O1_I1(r, r); > > diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc > index dc2b487844..e5fe15c338 100644 > --- a/tcg/riscv/tcg-target.c.inc > +++ b/tcg/riscv/tcg-target.c.inc > @@ -2630,7 +2630,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > default: > @@ -2877,7 +2876,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > case INDEX_op_extrh_i64_i32: > - case INDEX_op_ext_i32_i64: > return C_O1_I1(r, r); > > case INDEX_op_st8_i32: > diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc > index ab178bebc8..5c5a38c2c8 100644 > --- a/tcg/s390x/tcg-target.c.inc > +++ b/tcg/s390x/tcg-target.c.inc > @@ -2997,7 +2997,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > default: > @@ -3471,7 +3470,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_st_i64: > return C_O0_I2(r, r); > > - case INDEX_op_ext_i32_i64: > case INDEX_op_extu_i32_i64: > return C_O1_I1(r, r); > > diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc > index 0f2bec21e9..e93ef8e7f2 100644 > --- a/tcg/sparc64/tcg-target.c.inc > +++ b/tcg/sparc64/tcg-target.c.inc > @@ -1883,7 +1883,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ > case INDEX_op_extu_i32_i64: > default: > g_assert_not_reached(); > @@ -1909,7 +1908,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_ld32u_i64: > case INDEX_op_ld32s_i64: > case INDEX_op_ld_i64: > - case INDEX_op_ext_i32_i64: > case INDEX_op_extu_i32_i64: > case INDEX_op_qemu_ld_i32: > case INDEX_op_qemu_ld_i64: > diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc > index 9ba108ef8d..ecff90404f 100644 > --- a/tcg/tci/tcg-target.c.inc > +++ b/tcg/tci/tcg-target.c.inc > @@ -55,7 +55,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) > case INDEX_op_ld32u_i64: > case INDEX_op_ld32s_i64: > case INDEX_op_ld_i64: > - case INDEX_op_ext_i32_i64: > case INDEX_op_extu_i32_i64: > return C_O1_I1(r, r); > > @@ -1109,7 +1108,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ > case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ > - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ > case INDEX_op_extu_i32_i64: > case INDEX_op_extrl_i64_i32: > default: Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
diff --git a/tcg/tcg.c b/tcg/tcg.c index e688cd12b7..35f192e483 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1068,6 +1068,23 @@ QEMU_BUILD_BUG_ON((int)(offsetof(CPUNegativeOffsetState, tlb.f[0]) - < MIN_TLB_MASK_TABLE_OFS); #endif +#if TCG_TARGET_REG_BITS == 64 +/* + * We require these functions for slow-path function calls. + * Adapt them generically for opcode output. + */ + +static void tgen_exts_i32_i64(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) +{ + tcg_out_exts_i32_i64(s, a0, a1); +} + +static const TCGOutOpUnary outop_exts_i32_i64 = { + .base.static_constraint = C_O1_I1(r, r), + .out_rr = tgen_exts_i32_i64, +}; +#endif + /* * Register V as the TCGOutOp for O. * This verifies that V is of type T, otherwise give a nice compiler error. @@ -1122,6 +1139,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = { OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2), #else OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), + OUTOP(INDEX_op_ext_i32_i64, TCGOutOpUnary, outop_exts_i32_i64), #endif }; @@ -5409,9 +5427,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* emit instruction */ TCGType type = TCGOP_TYPE(op); switch (op->opc) { - case INDEX_op_ext_i32_i64: - tcg_out_exts_i32_i64(s, new_args[0], new_args[1]); - break; case INDEX_op_extu_i32_i64: tcg_out_extu_i32_i64(s, new_args[0], new_args[1]); break; @@ -5474,6 +5489,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) break; case INDEX_op_bswap64: + case INDEX_op_ext_i32_i64: assert(TCG_TARGET_REG_BITS == 64); /* fall through */ case INDEX_op_ctpop: diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 00400f6ea7..68f7a1cec2 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -2710,7 +2710,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType ext, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: default: @@ -3177,7 +3176,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: return C_O1_I1(r, r); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 6a5414ab3a..14b912beb7 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -3413,7 +3413,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: default: @@ -4001,7 +4000,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_extrh_i64_i32: return C_O1_I1(r, 0); - case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: return C_O1_I1(r, r); diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index c88db7a0e2..e2dbd08e12 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -1931,7 +1931,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: default: @@ -2462,7 +2461,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - case INDEX_op_ext_i32_i64: case INDEX_op_ld8s_i32: case INDEX_op_ld8s_i64: case INDEX_op_ld8u_i32: diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 56c58bf82d..e992a468eb 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -2364,7 +2364,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: default: @@ -2391,7 +2390,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_ld32s_i64: case INDEX_op_ld32u_i64: case INDEX_op_ld_i64: - case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 3d1ffa9130..fea767573c 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -3640,7 +3640,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: default: @@ -4270,7 +4269,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: return C_O1_I1(r, r); diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index dc2b487844..e5fe15c338 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -2630,7 +2630,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: default: @@ -2877,7 +2876,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: case INDEX_op_extrh_i64_i32: - case INDEX_op_ext_i32_i64: return C_O1_I1(r, r); case INDEX_op_st8_i32: diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index ab178bebc8..5c5a38c2c8 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -2997,7 +2997,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: default: @@ -3471,7 +3470,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_st_i64: return C_O0_I2(r, r); - case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: return C_O1_I1(r, r); diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 0f2bec21e9..e93ef8e7f2 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1883,7 +1883,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_extu_i32_i64: default: g_assert_not_reached(); @@ -1909,7 +1908,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: case INDEX_op_qemu_ld_i32: case INDEX_op_qemu_ld_i64: diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 9ba108ef8d..ecff90404f 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -55,7 +55,6 @@ tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) case INDEX_op_ld32u_i64: case INDEX_op_ld32s_i64: case INDEX_op_ld_i64: - case INDEX_op_ext_i32_i64: case INDEX_op_extu_i32_i64: return C_O1_I1(r, r); @@ -1109,7 +1108,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, case INDEX_op_call: /* Always emitted via tcg_out_call. */ case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ - case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ case INDEX_op_extu_i32_i64: case INDEX_op_extrl_i64_i32: default:
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- tcg/tcg.c | 22 +++++++++++++++++++--- tcg/aarch64/tcg-target.c.inc | 2 -- tcg/i386/tcg-target.c.inc | 2 -- tcg/loongarch64/tcg-target.c.inc | 2 -- tcg/mips/tcg-target.c.inc | 2 -- tcg/ppc/tcg-target.c.inc | 2 -- tcg/riscv/tcg-target.c.inc | 2 -- tcg/s390x/tcg-target.c.inc | 2 -- tcg/sparc64/tcg-target.c.inc | 2 -- tcg/tci/tcg-target.c.inc | 2 -- 10 files changed, 19 insertions(+), 21 deletions(-)