From patchwork Thu Apr 24 00:49:25 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 883921 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp3209784wrs; Wed, 23 Apr 2025 18:31:15 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCXFYHCZe8WdG+4Qe0vDdG761b+Le71pzKultuVWO8TezfWX0F0Dvjy73P35BRsEF0rxMKiPgQ==@linaro.org X-Google-Smtp-Source: AGHT+IG9W8UuaU6u8uDzuLGn9nBasUnz2fY1yw9fb7YJK4qojYLGj3gXfF0UiTmfrZBlmc+reRZv X-Received: by 2002:ac8:584c:0:b0:476:a74d:f23b with SMTP id d75a77b69052e-47eb52c26afmr8990491cf.48.1745458275502; Wed, 23 Apr 2025 18:31:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745458275; cv=none; d=google.com; s=arc-20240605; b=JeeWSLEnTiYiNFF6cOVBonCK2wLbzBUvvmBbs83JpXkEK7+jbSj+NYgMi9zEUbUEX/ FLBx9oAQfzJhEIUfgBVMmeKCirJ4dG5v9ABs1bEAdtHyv2yxllEv+uAent/69Hl7VIES Y9yg2gI64CPe1uMlpl6NFK4ySFShWol6UsfkasAGeWVmEsJcVX4CSMB+hEWFH4+Jjlbm 9MlhLOnz371yew0h+zSX6pQuHRDOTvoPpvcyFtKpnbnjuvZ1azKaM0nFaH0tXTdHUEar jNsKEZsWozFWadk9Z/i957LpXlGAQWbAPaT7cXIzwC5dPeqAYy1kgUgI9fZwptpGNOc2 PKrA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7VXEDUlPkpIMjb0Jt+mGuDdJy2bXxmmNFXU1sXIXZA4=; fh=kQadAhxV42GJ3cd2VUw1RyURv/zJQGvmUdF7iLEVTtc=; b=ZGiexuAUOSSspDujP9FN1LNkvCtzOf9EEErUZSrCMwrtVV7oml+U7vGBL62Uy8RIl2 ZHoAEYjchncEJ+m8og8BEMlJ1fbbwniiFn0EvnviZ8/G+2UOw6DJYOTmY88hRQAQPpd0 sXYmhpnuXBCdmnW+9O5e8vcgdnNeuHqIAYrIYffVw2ZBnj+/kLhtdgeZ1n8xK8jLkCE4 uBaXDSuHGDg/emHdcU9JSGIOHXnh21YbPBH9/X/w7rB05N/phvxQfjGiuuixAEfV0MSy CxNncWmLC1dc9JVp8OnwR1R8uipM0tr+DUTj15WC9PE1rSVWlUXZ6CnRG+0qOahOjdMz 9JwA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B5hnbVZ4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d75a77b69052e-47ea25ae719si5484151cf.546.2025.04.23.18.31.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 23 Apr 2025 18:31:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B5hnbVZ4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u7l0V-0003LN-RG; Wed, 23 Apr 2025 21:04:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u7kwz-0005Wl-5N for qemu-devel@nongnu.org; Wed, 23 Apr 2025 21:00:25 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u7kwt-0005XC-V2 for qemu-devel@nongnu.org; Wed, 23 Apr 2025 21:00:24 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-73bf5aa95e7so372361b3a.1 for ; Wed, 23 Apr 2025 18:00:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745456418; x=1746061218; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7VXEDUlPkpIMjb0Jt+mGuDdJy2bXxmmNFXU1sXIXZA4=; b=B5hnbVZ4rGdEq8Gqve76Rt/gtItWKv3I/e1LvIRMNZDax0AW3WI6bzFMogiMgvqAOw Idl8AVtIo/yT2eHxzoPezNW8w2ua12I+x11MX6EQEMusLCZ0/nwdGzO9e+FLzJ66HN9c Yld6AgiNEn1MnUOwsw2n9g+5suHg9IqNQAWF/X9Llzt2CxKcNng9A/FXsDyqjJ54Kkwl kBMmZMEjebdnL+ONrn2qkTgVIsg98c5V9LHQbtJ4NifhhRamqSvIh9e4ruDQ5oyJnFxm EtsEnVoUL5+xDLWlLDNpcJqzusLofpNl9Og4jxbxrY9m0I9tvAsu18N3SRCIx0ydMEpL efIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745456418; x=1746061218; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7VXEDUlPkpIMjb0Jt+mGuDdJy2bXxmmNFXU1sXIXZA4=; b=NkFZK3aO1DW//kSvv6RJNpp25gVDM01lmt8MTNG+wCGHNlMtbqwEFjexqBPpftkgBX cqUTtL8IzdTYw7GqreSjswYPBzQX1yiiVyMU/Dj/VYij7gDOqKCcchpPl3fKiR2F7zzZ vMBij4SSjKENkSUYs/nDR9K4MPoNjaFOE7uBOUn1yZ/3YGWOS8JL3tP9mMjychzCpfeR +tdzybIVhHaXrui/OjT2pTpToexscdPED4I8Nj9UawlszVIXzSTYTtS89p/YpBSunIrY b9IGbsZQBZ+QHnlST3t0uA9VcNw86pLK9QVAjTz00kti01ge4TdCDUl9+ocKR5sNyIyt YcUA== X-Gm-Message-State: AOJu0YycQVECBjpur/a2+KayIbwTw1/SKZ6ntv1z9JrBZSFVkzwKfNzD 7+9jL/4ui3xkxY7qdb4vblUqjgoPVKIskHYpjpUR8xkhK+wDAOw/aLbDiSVlyjHpap59GfXVWV5 w X-Gm-Gg: ASbGncuxvRaZ8eLCCJmAoSgaXv7Z0bOGDrc2orFg1sUf42SjReB15f3JiK2lzRV2561 8Y1C58uidUT0Lu6b7MAvr6te3xEyDUr0GJDovnYyRbcqv1owQ/TdcJxNKB/fBh7L3t6KtrexYuu B5xfNCPBhcxo2QAeLg9DPRbHPyGax6QnWFPXFuZKnM+HOkXtX5+xYNCIjcRhP/UxDepQCqe/pGm x+pRFl2UNjM8GVGNCXuDPeRpcVCqkKFV2KrMobMPdH8QkEjIqxJhR+rKUOkSsnhaGiDPo6PMbXC uF8X42zazMKTQg9a2EDf5LotDojK9cSwlHohT2UcmGgO+Ukpt54pW49EBON5vqSeXNMGAZX79+g yH7SeW/aAog== X-Received: by 2002:a05:6a20:c70e:b0:1f5:57d0:7014 with SMTP id adf61e73a8af0-20444f23718mr934259637.25.1745456418182; Wed, 23 Apr 2025 18:00:18 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15f76f45c7sm129259a12.16.2025.04.23.18.00.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 18:00:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 140/148] tcg: Move cpu_req_mo() macro to target-agnostic 'backend-ldst.h' Date: Wed, 23 Apr 2025 17:49:25 -0700 Message-ID: <20250424004934.598783-141-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250424004934.598783-1-richard.henderson@linaro.org> References: <20250424004934.598783-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/backend-ldst.h | 41 +++++++++++++++++++++++++++++++++++++ accel/tcg/internal-target.h | 28 ------------------------- accel/tcg/cputlb.c | 1 + accel/tcg/user-exec.c | 1 + 4 files changed, 43 insertions(+), 28 deletions(-) create mode 100644 accel/tcg/backend-ldst.h diff --git a/accel/tcg/backend-ldst.h b/accel/tcg/backend-ldst.h new file mode 100644 index 0000000000..9c3a407a5a --- /dev/null +++ b/accel/tcg/backend-ldst.h @@ -0,0 +1,41 @@ +/* + * Internal memory barrier helpers for QEMU (target agnostic) + * + * Copyright (c) 2003 Fabrice Bellard + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef ACCEL_TCG_BACKEND_LDST_H +#define ACCEL_TCG_BACKEND_LDST_H + +#include "tcg-target-mo.h" + +/** + * tcg_req_mo: + * @guest_mo: Guest default memory order + * @type: TCGBar + * + * Filter @type to the barrier that is required for the guest + * memory ordering vs the host memory ordering. A non-zero + * result indicates that some barrier is required. + */ +#define tcg_req_mo(guest_mo, type) \ + ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) + +/** + * cpu_req_mo: + * @cpu: CPUState + * @type: TCGBar + * + * If tcg_req_mo indicates a barrier for @type is required + * for the guest memory model, issue a host memory barrier. + */ +#define cpu_req_mo(cpu, type) \ + do { \ + if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \ + smp_mb(); \ + } \ + } while (0) + +#endif diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index f5a3fd7e40..9a9cef3140 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -13,7 +13,6 @@ #include "exec/exec-all.h" #include "exec/translation-block.h" #include "tb-internal.h" -#include "tcg-target-mo.h" #include "exec/mmap-lock.h" /* @@ -44,31 +43,4 @@ void page_table_config_init(void); G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); #endif /* CONFIG_USER_ONLY */ -/** - * tcg_req_mo: - * @guest_mo: Guest default memory order - * @type: TCGBar - * - * Filter @type to the barrier that is required for the guest - * memory ordering vs the host memory ordering. A non-zero - * result indicates that some barrier is required. - */ -#define tcg_req_mo(guest_mo, type) \ - ((type) & guest_mo & ~TCG_TARGET_DEFAULT_MO) - -/** - * cpu_req_mo: - * @cpu: CPUState - * @type: TCGBar - * - * If tcg_req_mo indicates a barrier for @type is required - * for the guest memory model, issue a host memory barrier. - */ -#define cpu_req_mo(cpu, type) \ - do { \ - if (tcg_req_mo(cpu->cc->tcg_ops->guest_default_memory_order, type)) { \ - smp_mb(); \ - } \ - } while (0) - #endif /* ACCEL_TCG_INTERNAL_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 35b1ff03a5..d9fb68d719 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -48,6 +48,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 3f4d682446..5eef8e7f18 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -37,6 +37,7 @@ #include "qemu/int128.h" #include "trace.h" #include "tcg/tcg-ldst.h" +#include "backend-ldst.h" #include "internal-common.h" #include "internal-target.h" #include "tb-internal.h"