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[71.212.47.143]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-73e25a6a971sm209353b3a.103.2025.04.23.17.53.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 23 Apr 2025 17:53:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PULL 063/148] accel/tcg: Fix argument types of tlb_reset_dirty Date: Wed, 23 Apr 2025 17:48:08 -0700 Message-ID: <20250424004934.598783-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250424004934.598783-1-richard.henderson@linaro.org> References: <20250424004934.598783-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The arguments to tlb_reset_dirty are host pointers. The conversion from ram_addr_t was done in the sole caller, tlb_reset_dirty_range_all. Fixes: e554861766d ("exec: prepare for splitting") Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cputlb.h | 2 +- accel/tcg/cputlb.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 8125f6809c..03ed7e2165 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -31,7 +31,7 @@ void tlb_unprotect_code(ram_addr_t ram_addr); #endif #ifndef CONFIG_USER_ONLY -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); +void tlb_reset_dirty(CPUState *cpu, uintptr_t start, uintptr_t length); void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length); #endif diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b2db49e305..10090067f7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -912,7 +912,7 @@ static inline void copy_tlb_helper_locked(CPUTLBEntry *d, const CPUTLBEntry *s) * We must take tlb_c.lock to avoid racing with another vCPU update. The only * thing actually updated is the target TLB entry ->addr_write flags. */ -void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) +void tlb_reset_dirty(CPUState *cpu, uintptr_t start, uintptr_t length) { int mmu_idx; @@ -923,12 +923,12 @@ void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length) for (i = 0; i < n; i++) { tlb_reset_dirty_range_locked(&cpu->neg.tlb.f[mmu_idx].table[i], - start1, length); + start, length); } for (i = 0; i < CPU_VTLB_SIZE; i++) { tlb_reset_dirty_range_locked(&cpu->neg.tlb.d[mmu_idx].vtable[i], - start1, length); + start, length); } } qemu_spin_unlock(&cpu->neg.tlb.c.lock);