From patchwork Fri Apr 25 21:53:23 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 884795 Delivered-To: patch@linaro.org Received: by 2002:a5d:474d:0:b0:38f:210b:807b with SMTP id o13csp4190604wrs; Fri, 25 Apr 2025 15:39:06 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCVmIhflGCn40VQymTrdjxTaQ4PajnxBFD+333pB56X7iJY5bmrNBgPRWglIedGc8e+CTw/yvA==@linaro.org X-Google-Smtp-Source: AGHT+IG0j+2RR0sffX9fTq8zs3vjxyECtEwu6iSwnE4RJIZ4LwkEgWGH7SvW8kFqQCJXanjc6aHV X-Received: by 2002:a05:620a:2596:b0:7c5:ad56:46c6 with SMTP id af79cd13be357-7c9612d18b2mr621782785a.2.1745620745980; Fri, 25 Apr 2025 15:39:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1745620745; cv=none; d=google.com; s=arc-20240605; b=ARrFuS3wZ4hNDrBwFQTxKLJwajf/399lnPhmQbtn9/rsOLEwnc5hGNprTHrVRO+Ap5 /DGrW8oCudkjhB1VdZZLC8LMAEOFxGGoWY6ZfJ4HLS8/D1M2Efwy5IMEmYjKJZljzdFY p8S1u/1aEMXd+9zx9WoHsFzDsNo/8L4EyiwpQ9DTGx6dy4iTSkzG9hS+vsj5OdDejEee DMDou160j39MevGlp/sXBWvn53RK7EvmPbAkdr/wFCWzRedJh02Glbp6dpH+abyU21pT 08jmlzJit/yWfrwn7ayOSQgb5HzUR1KjcazOK4hbLKhz8shecmj2TqQlcpASd+wjDKc7 zrnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cYqMPpyityblyyTyL7tCV6mfbRZ+U/cmBtqtXpPhz3o=; fh=kQadAhxV42GJ3cd2VUw1RyURv/zJQGvmUdF7iLEVTtc=; b=L5rNgbNoy9A3LmJJsk25Ktzofp5/mxK/bg8q0Dfa2fc/erRxU7Z9MQLEsKJO8NE0+k LmXUmgM3cMCeEL8UJtkpW0XuMC6aXy6Km+p12qglnbiiSWcfH0qDotiqA2vBLXV19a0W 0QGoAk6fxGDdSOfsF41OOMb86tImqtGHNGrjXWHe5z0iE1r2NKCZQGN3jxYnySMA9XcV M4ynW+vC3IfTnswlDavt7qslC1Qf5o5ltyX0DwG7RufRB2HJI9YoNgRyXVI6tv4QLZz3 LA8R8IyC/UVs2Xx8WTs2ZV+J8QIzU3SNz1c0tqpF/9fhbaMKHMIO4DHNqT485NIZ4CXa yEQA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=czBJ+1uG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id af79cd13be357-7c958c9f14fsi466149785a.2.2025.04.25.15.39.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 25 Apr 2025 15:39:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=czBJ+1uG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1u8R53-0004fV-08; Fri, 25 Apr 2025 17:59:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1u8R4P-0001xx-1e for qemu-devel@nongnu.org; Fri, 25 Apr 2025 17:58:53 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1u8R4M-0000sC-HR for qemu-devel@nongnu.org; Fri, 25 Apr 2025 17:58:52 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-227914acd20so33748065ad.1 for ; Fri, 25 Apr 2025 14:58:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1745618329; x=1746223129; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cYqMPpyityblyyTyL7tCV6mfbRZ+U/cmBtqtXpPhz3o=; b=czBJ+1uGRi5meUV+BIjoKAcBqmUWNfHtEvmGKEQFo974hIbVQkTWyTAjEdeFGjyRXm wNT1Leb3op0ZtWf8AdTkpoIyYMaotU3LWSjSxrsRy1eVjoACSRoVwfHNxTzKxHaoFKU0 mZNzi399Qeejz15zR6bL15KrGgNxVLv8a+RBaucJIqzwcsfdU7qt9Bzf1zg8+80tWaYi fkR2TrdDCTfUk3mBnefzUwd7QjQVcyzNMdmhFfyZ9n/8BdYtdjPo4kfA4iCs8ltqGjUy SK2llKCYRx/i+BigI6byHoRCjCMrWWd/aDWuHdsJa/qJrcD7CeTnk4ws7JG82gASSFZ8 GsKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1745618329; x=1746223129; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cYqMPpyityblyyTyL7tCV6mfbRZ+U/cmBtqtXpPhz3o=; b=iTw0ef14Qeout0VJHKUY1FaExvZHAKmuviiOV50IdUYWQpWwQRfmPCmFIIIXaWRL3A tgAfU7e9WpJ3vOHoJnq36tU97O1ZywQxZKsVWniKXYYPniiEDx9O7s3p8jyHAXZnWEyd zN9gsLYEa6XISSzI4E9TCmIiDC6WjKPyjWwYbkbztPyfbPhuoo+djHDM0OWcLNXW+Gv7 9lOEYzNuXs4UcA9tcdjophvkyU6COes3Jl/wdVIU5Qhkd7zdUdFqkkmxTdZ0xnIvBCGx 03P5VAOzPJUoJI/XNPs7jQR1qzXhREbRzZl0guLIxJ+31L2k2ALTvY7+J82jnrFahuCo fqfA== X-Gm-Message-State: AOJu0YyhNFawRi7XS7xl9WGmue9h3t5lHfP8TfQYMzohr7Q+lQxpu1fA NxHH3MyQtABE0Wm3SWOUNBOy5DgdMvLxhml2eBh3mveR2xa52cAXrbMWnommZkpzeaUT4m7+HfP S X-Gm-Gg: ASbGnctW4BgNjqeKm+pxsaKBz8IJeTAlMMAlzlE0ls8+un/2O4xdKQXBDA80iV/33CZ 3Nah7pf2BbwwZfLidr8ENIOuSJPeyGBRxAfItXa6jhg296FIInZzD4pMGn975lpUrjccsNSJiVt HNMvqfAdd4PWOz2cXfxZrEnI1upDbs59WVg9cwUi4UpDNHzbkxDBdsPzEpgsME2i3yK/hJK0JOZ Zbk6Nwq01wUn95Stp4xf2dRfc614rwN1h9g5oYtcDw+n4y4x14g+hDAMTT4F0uLYEdWsvTMZ5c9 OKC09JuCnlmArsHDBPQ+HdjZ2dI6/3lLWAp/odQh3lkuufs2r6zmxSWJN6TpRaoZ+xrzuSRA204 /6s44A4n7HQ== X-Received: by 2002:a17:903:f87:b0:223:4d5e:7592 with SMTP id d9443c01a7336-22db4996560mr112165715ad.21.1745618328820; Fri, 25 Apr 2025 14:58:48 -0700 (PDT) Received: from stoup.. (71-212-47-143.tukw.qwest.net. [71.212.47.143]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-22db4d770d6sm37749595ad.17.2025.04.25.14.58.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Apr 2025 14:58:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 069/159] tcg: Merge INDEX_op_ctz_{i32,i64} Date: Fri, 25 Apr 2025 14:53:23 -0700 Message-ID: <20250425215454.886111-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250425215454.886111-1-richard.henderson@linaro.org> References: <20250425215454.886111-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h | 3 +-- tcg/optimize.c | 10 +++++----- tcg/tcg-op.c | 16 ++++++++-------- tcg/tcg.c | 6 ++---- tcg/tci.c | 4 ++-- docs/devel/tcg-ops.rst | 2 +- tcg/tci/tcg-target.c.inc | 2 +- 7 files changed, 20 insertions(+), 23 deletions(-) diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index ad1d193ef4..4dfd8708a5 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -43,6 +43,7 @@ DEF(add, 1, 2, 0, TCG_OPF_INT) DEF(and, 1, 2, 0, TCG_OPF_INT) DEF(andc, 1, 2, 0, TCG_OPF_INT) DEF(clz, 1, 2, 0, TCG_OPF_INT) +DEF(ctz, 1, 2, 0, TCG_OPF_INT) DEF(divs, 1, 2, 0, TCG_OPF_INT) DEF(divs2, 2, 3, 0, TCG_OPF_INT) DEF(divu, 1, 2, 0, TCG_OPF_INT) @@ -96,7 +97,6 @@ DEF(setcond2_i32, 1, 4, 1, 0) DEF(bswap16_i32, 1, 1, 1, 0) DEF(bswap32_i32, 1, 1, 1, 0) -DEF(ctz_i32, 1, 2, 0, 0) DEF(ctpop_i32, 1, 1, 0, 0) DEF(setcond_i64, 1, 2, 1, 0) @@ -130,7 +130,6 @@ DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) DEF(bswap16_i64, 1, 1, 1, 0) DEF(bswap32_i64, 1, 1, 1, 0) DEF(bswap64_i64, 1, 1, 1, 0) -DEF(ctz_i64, 1, 2, 0, 0) DEF(ctpop_i64, 1, 1, 0, 0) DEF(add2_i64, 2, 4, 0, 0) diff --git a/tcg/optimize.c b/tcg/optimize.c index d8d0e728aa..af4e76e81b 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -509,10 +509,10 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type, } return x ? clz64(x) : y; - case INDEX_op_ctz_i32: - return (uint32_t)x ? ctz32(x) : y; - - case INDEX_op_ctz_i64: + case INDEX_op_ctz: + if (type == TCG_TYPE_I32) { + return (uint32_t)x ? ctz32(x) : y; + } return x ? ctz64(x) : y; case INDEX_op_ctpop_i32: @@ -2899,7 +2899,7 @@ void tcg_optimize(TCGContext *s) done = fold_bswap(&ctx, op); break; case INDEX_op_clz: - CASE_OP_32_64(ctz): + case INDEX_op_ctz: done = fold_count_zeros(&ctx, op); break; CASE_OP_32_64(ctpop): diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index b117a59f05..7bf7de1213 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -750,11 +750,11 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { TCGv_i32 z, t; - if (tcg_op_supported(INDEX_op_ctz_i32, TCG_TYPE_I32, 0)) { - tcg_gen_op3_i32(INDEX_op_ctz_i32, ret, arg1, arg2); + if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)) { + tcg_gen_op3_i32(INDEX_op_ctz, ret, arg1, arg2); return; } - if (tcg_op_supported(INDEX_op_ctz_i64, TCG_TYPE_I64, 0)) { + if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)) { TCGv_i64 t1 = tcg_temp_ebb_new_i64(); TCGv_i64 t2 = tcg_temp_ebb_new_i64(); tcg_gen_extu_i32_i64(t1, arg1); @@ -788,7 +788,7 @@ void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) { - if (!tcg_op_supported(INDEX_op_ctz_i32, TCG_TYPE_I32, 0) + if (!tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0) && TCG_TARGET_HAS_ctpop_i32 && arg2 == 32) { /* This equivalence has the advantage of not requiring a fixup. */ TCGv_i32 t = tcg_temp_ebb_new_i32(); @@ -2366,8 +2366,8 @@ void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) { TCGv_i64 z, t; - if (tcg_op_supported(INDEX_op_ctz_i64, TCG_TYPE_I64, 0)) { - tcg_gen_op3_i64(INDEX_op_ctz_i64, ret, arg1, arg2); + if (tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0)) { + tcg_gen_op3_i64(INDEX_op_ctz, ret, arg1, arg2); return; } if (TCG_TARGET_HAS_ctpop_i64) { @@ -2395,7 +2395,7 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) { if (TCG_TARGET_REG_BITS == 32 && arg2 <= 0xffffffffu - && tcg_op_supported(INDEX_op_ctz_i32, TCG_TYPE_I32, 0)) { + && tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I32, 0)) { TCGv_i32 t32 = tcg_temp_ebb_new_i32(); tcg_gen_ctzi_i32(t32, TCGV_HIGH(arg1), arg2 - 32); tcg_gen_addi_i32(t32, t32, 32); @@ -2403,7 +2403,7 @@ void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) tcg_gen_movi_i32(TCGV_HIGH(ret), 0); tcg_temp_free_i32(t32); } else if (arg2 == 64 - && !tcg_op_supported(INDEX_op_ctz_i64, TCG_TYPE_I64, 0) + && !tcg_op_supported(INDEX_op_ctz, TCG_TYPE_I64, 0) && TCG_TARGET_HAS_ctpop_i64) { /* This equivalence has the advantage of not requiring a fixup. */ TCGv_i64 t = tcg_temp_ebb_new_i64(); diff --git a/tcg/tcg.c b/tcg/tcg.c index 3f610e3f83..18b28a670e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1027,8 +1027,7 @@ static const TCGOutOp * const all_outop[NB_OPS] = { OUTOP(INDEX_op_and, TCGOutOpBinary, outop_and), OUTOP(INDEX_op_andc, TCGOutOpBinary, outop_andc), OUTOP(INDEX_op_clz, TCGOutOpBinary, outop_clz), - OUTOP(INDEX_op_ctz_i32, TCGOutOpBinary, outop_ctz), - OUTOP(INDEX_op_ctz_i64, TCGOutOpBinary, outop_ctz), + OUTOP(INDEX_op_ctz, TCGOutOpBinary, outop_ctz), OUTOP(INDEX_op_divs, TCGOutOpBinary, outop_divs), OUTOP(INDEX_op_divu, TCGOutOpBinary, outop_divu), OUTOP(INDEX_op_divs2, TCGOutOpDivRem, outop_divs2), @@ -5400,8 +5399,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) case INDEX_op_and: case INDEX_op_andc: case INDEX_op_clz: - case INDEX_op_ctz_i32: - case INDEX_op_ctz_i64: + case INDEX_op_ctz: case INDEX_op_divs: case INDEX_op_divu: case INDEX_op_eqv: diff --git a/tcg/tci.c b/tcg/tci.c index b505944b10..550f2014a8 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -735,7 +735,7 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env, tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] ? clz64(regs[r1]) : regs[r2]; break; - case INDEX_op_ctz_i64: + case INDEX_op_ctz: tci_args_rrr(insn, &r0, &r1, &r2); regs[r0] = regs[r1] ? ctz64(regs[r1]) : regs[r2]; break; @@ -1049,6 +1049,7 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_and: case INDEX_op_andc: case INDEX_op_clz: + case INDEX_op_ctz: case INDEX_op_divs: case INDEX_op_divu: case INDEX_op_eqv: @@ -1066,7 +1067,6 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info) case INDEX_op_shr: case INDEX_op_sub: case INDEX_op_xor: - case INDEX_op_ctz_i64: case INDEX_op_tci_ctz32: case INDEX_op_tci_clz32: case INDEX_op_tci_divs32: diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 22f0432988..92344b8786 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -362,7 +362,7 @@ Logical - | *t0* = *t1* ? clz(*t1*) : *t2* - * - ctz_i32/i64 *t0*, *t1*, *t2* + * - ctz *t0*, *t1*, *t2* - | *t0* = *t1* ? ctz(*t1*) : *t2* diff --git a/tcg/tci/tcg-target.c.inc b/tcg/tci/tcg-target.c.inc index 47bdec5f44..d8d45e2c4b 100644 --- a/tcg/tci/tcg-target.c.inc +++ b/tcg/tci/tcg-target.c.inc @@ -645,7 +645,7 @@ static void tgen_ctz(TCGContext *s, TCGType type, { TCGOpcode opc = (type == TCG_TYPE_I32 ? INDEX_op_tci_ctz32 - : INDEX_op_ctz_i64); + : INDEX_op_ctz); tcg_out_op_rrr(s, opc, a0, a1, a2); }