diff mbox series

[v2,10/10] target/microblaze: Simplify compute_ldst_addr_type{a, b}

Message ID 20250525160220.222154-11-richard.henderson@linaro.org
State New
Headers show
Series target/microblaze: Always use TARGET_LONG_BITS == 32 | expand

Commit Message

Richard Henderson May 25, 2025, 4:02 p.m. UTC
Require TCGv_i32 and TCGv be identical, so drop
the extensions.  Return constants when possible
instead of a mov into a temporary.  Return register
inputs unchanged when possible.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/translate.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

Comments

Edgar E. Iglesias May 25, 2025, 7:40 p.m. UTC | #1
On Sun, May 25, 2025 at 05:02:20PM +0100, Richard Henderson wrote:
> Require TCGv_i32 and TCGv be identical, so drop
> the extensions.  Return constants when possible
> instead of a mov into a temporary.  Return register
> inputs unchanged when possible.
> 
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>



> ---
>  target/microblaze/translate.c | 26 +++++++++++++-------------
>  1 file changed, 13 insertions(+), 13 deletions(-)
> 
> diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
> index 047d97e2c5..5098a1db4d 100644
> --- a/target/microblaze/translate.c
> +++ b/target/microblaze/translate.c
> @@ -606,19 +606,18 @@ DO_TYPEBI(xori, false, tcg_gen_xori_i32)
>  
>  static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
>  {
> -    TCGv ret = tcg_temp_new();
> +    TCGv ret;
>  
>      /* If any of the regs is r0, set t to the value of the other reg.  */
>      if (ra && rb) {
> -        TCGv_i32 tmp = tcg_temp_new_i32();
> -        tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]);
> -        tcg_gen_extu_i32_tl(ret, tmp);
> +        ret = tcg_temp_new_i32();
> +        tcg_gen_add_i32(ret, cpu_R[ra], cpu_R[rb]);
>      } else if (ra) {
> -        tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
> +        ret = cpu_R[ra];
>      } else if (rb) {
> -        tcg_gen_extu_i32_tl(ret, cpu_R[rb]);
> +        ret = cpu_R[rb];
>      } else {
> -        tcg_gen_movi_tl(ret, 0);
> +        ret = tcg_constant_i32(0);
>      }
>  
>      if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {
> @@ -629,15 +628,16 @@ static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
>  
>  static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
>  {
> -    TCGv ret = tcg_temp_new();
> +    TCGv ret;
>  
>      /* If any of the regs is r0, set t to the value of the other reg.  */
> -    if (ra) {
> -        TCGv_i32 tmp = tcg_temp_new_i32();
> -        tcg_gen_addi_i32(tmp, cpu_R[ra], imm);
> -        tcg_gen_extu_i32_tl(ret, tmp);
> +    if (ra && imm) {
> +        ret = tcg_temp_new_i32();
> +        tcg_gen_addi_i32(ret, cpu_R[ra], imm);
> +    } else if (ra) {
> +        ret = cpu_R[ra];
>      } else {
> -        tcg_gen_movi_tl(ret, (uint32_t)imm);
> +        ret = tcg_constant_i32(imm);
>      }
>  
>      if (ra == 1 && dc->cfg->stackprot) {
> -- 
> 2.43.0
>
diff mbox series

Patch

diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 047d97e2c5..5098a1db4d 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -606,19 +606,18 @@  DO_TYPEBI(xori, false, tcg_gen_xori_i32)
 
 static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
 {
-    TCGv ret = tcg_temp_new();
+    TCGv ret;
 
     /* If any of the regs is r0, set t to the value of the other reg.  */
     if (ra && rb) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_add_i32(tmp, cpu_R[ra], cpu_R[rb]);
-        tcg_gen_extu_i32_tl(ret, tmp);
+        ret = tcg_temp_new_i32();
+        tcg_gen_add_i32(ret, cpu_R[ra], cpu_R[rb]);
     } else if (ra) {
-        tcg_gen_extu_i32_tl(ret, cpu_R[ra]);
+        ret = cpu_R[ra];
     } else if (rb) {
-        tcg_gen_extu_i32_tl(ret, cpu_R[rb]);
+        ret = cpu_R[rb];
     } else {
-        tcg_gen_movi_tl(ret, 0);
+        ret = tcg_constant_i32(0);
     }
 
     if ((ra == 1 || rb == 1) && dc->cfg->stackprot) {
@@ -629,15 +628,16 @@  static TCGv compute_ldst_addr_typea(DisasContext *dc, int ra, int rb)
 
 static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm)
 {
-    TCGv ret = tcg_temp_new();
+    TCGv ret;
 
     /* If any of the regs is r0, set t to the value of the other reg.  */
-    if (ra) {
-        TCGv_i32 tmp = tcg_temp_new_i32();
-        tcg_gen_addi_i32(tmp, cpu_R[ra], imm);
-        tcg_gen_extu_i32_tl(ret, tmp);
+    if (ra && imm) {
+        ret = tcg_temp_new_i32();
+        tcg_gen_addi_i32(ret, cpu_R[ra], imm);
+    } else if (ra) {
+        ret = cpu_R[ra];
     } else {
-        tcg_gen_movi_tl(ret, (uint32_t)imm);
+        ret = tcg_constant_i32(imm);
     }
 
     if (ra == 1 && dc->cfg->stackprot) {