From patchwork Sun May 25 16:02:16 2025 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 892467 Delivered-To: patch@linaro.org Received: by 2002:a5d:6e53:0:b0:3a3:61c9:c5d4 with SMTP id j19csp840440wrz; Sun, 25 May 2025 09:04:32 -0700 (PDT) X-Forwarded-Encrypted: i=2; AJvYcCWca4aD56rl5Y2DpK2pJ2pyLXEggT91+oKGnngsf254Sz1DQKOmyf1p7o5gA3EnVnI6PLJKNQ==@linaro.org X-Google-Smtp-Source: AGHT+IHsPJgVk9MsDSEyB03pX6hRPTX/CXGKiahcxSjUqcsZlAtppiis4tF2ENO8K0vp/YEvNFmO X-Received: by 2002:a05:6e02:12e8:b0:3db:72f7:d7b3 with SMTP id e9e14a558f8ab-3dc9b695249mr51638415ab.4.1748189072167; Sun, 25 May 2025 09:04:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1748189072; cv=none; d=google.com; s=arc-20240605; b=T+fqZz61XVB71FZrmwV05z1QClr9xyzGvMegN8lHPUZCOq/8MDaunmeMoDtI1ND5dl HbAh9xB1k7mz9IxNiEUjiWXQISjs7VY1FEtix0a4eK8qY3D91PgJ/+51jKv7jxA8ULGx hxcK16xVecvZA28XqMRvgBWnbiBqvy9Rw/iY53dkt5FceW2k3NEngXc0ggKFpJLmBENM K7s56zk8DLQkWWedVlgbCrQkjXbh3qd0ZT6BD2ETY/yV9KmeHi/TWzMpNEkkY0UeFkQr PMCJwIctB8R3UpICbm0Xjz+eo1x6P5LI/MyO+Uf0i36m5X24DgW4aDuwURkta+BBNGrS +IIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20240605; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qePmWWXgxnxC8EgpTPJrdJSihex1YCPIe/WXpW/iZ68=; fh=8mBO+FwhNjUD9ALhUxcYEwIlwc/hLQI6+6+QuDX34lg=; b=lhltxdk6FVNf4rLJc/Z76UTS7mNMrywANlrvI9vW/Ile1QNSjVgvZggCLQEDYOLuXu NBevHmTtZi21Hn8aIBWBNZhO3QNt5qVJSP02M7sy3aqzYg6ilESI3NpB0GixFD/vNYa2 xK3mRhGXriV8k/YiXgrYzLimaC7BefsPYrtKDwb7ZIGroP4bbg1KMvR/vNDlNHTyB7BU yr7s7TiTDCLjUn+acgN8pt2kTw/UdSQqWRmoF2DbgsLflppTY9Tsos125yDnmhOflSTI 72Hgt91JvgqVygEi5Wy4g2vOmZuSzYuq7qm37YkJiqBS0+yta6QaYEgDCWdGcHWm9FVm kIWA==; dara=google.com ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="H/Uwtqjn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 8926c6da1cb9f-4fc33d1cce7si2015374173.80.2025.05.25.09.04.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sun, 25 May 2025 09:04:32 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="H/Uwtqjn"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org; dara=neutral header.i=@linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uJDoT-00025k-Ab; Sun, 25 May 2025 12:03:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uJDo6-0001mf-J5 for qemu-devel@nongnu.org; Sun, 25 May 2025 12:02:40 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uJDo4-00036Z-JN for qemu-devel@nongnu.org; Sun, 25 May 2025 12:02:38 -0400 Received: by mail-wm1-x330.google.com with SMTP id 5b1f17b1804b1-441d1ed82dbso17636675e9.0 for ; Sun, 25 May 2025 09:02:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748188954; x=1748793754; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qePmWWXgxnxC8EgpTPJrdJSihex1YCPIe/WXpW/iZ68=; b=H/UwtqjncIN3h5/SVIpwEP/BLuSGikag6aHgg5go4AwuUdST9zTY6Z2J2bU7lhhP5j hLDpMWMdYiUfrqA1wveLwrlZsPZeNouspWEg8YryXudT5pSL/cLVS3cwLvP/ylsnjpXe 7QFNe/a1Yi24749s0HXrMPzzG5O5YP4YWONNuj9vfAIxVZOLTn01tA66wYbWWe/+1KNk 7s/v49y8pu1KJr2c0JacEoiTuXhwTNBZkuW5dAartVPzZytZqdj/jRI2+r5iiK9Z0FQL I+W59dShX/sXLk4VkTYya/+X8xvmlZroLcKhjs/bIX8504Mvo8EmpYLExToDkFuEpCsC SD1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748188954; x=1748793754; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qePmWWXgxnxC8EgpTPJrdJSihex1YCPIe/WXpW/iZ68=; b=Beem3aJELzoRDGQAYYdGfUoSxsjSuiec1WPlNStQTwKpbrT4CM+K4gKCzXGPBwahnS +HFKnXVzr4WxsoQD6tkdO1sLlmMdgsTFJc0PLcAp14RhcW+KpENnfF1nn97URNWinpeN HVQry7WxqADfTlI6tpp/apLxze4SYNxGW+65PyfQX56Lo5AvsoSWMNd23qXejpp0xmLR I7IqJCvCofFJzDeEY4mVQVXQw/OtkKDipSHgkUOCLv/c/p2OksKWZsmqDyc/TUfte/Gi ksKQZN+VkceEaEZF1MExsWA8DlUjOX3eCHo9YgLf7YPi5y/2SEFIibsTa9ASmQqimTvY GnyQ== X-Gm-Message-State: AOJu0YyhMdcxoH8moaNtSITsV9+VRSPYnTcc7MKrzL0mf4u3gEo0jQx5 jX4XVqWJCtS/li0ghT9aNOFK5yxtdlqujrPQN62uG8s47sJRC5M5/Zo7xVLEuJIj0MxE5sNQlZF lfx0i5D8= X-Gm-Gg: ASbGncsvbMyai+k1MnKcp0+GA+7SVEgJ+ONdoWokrKnEuYTeP50k4KBabe1Rxu2HFmj /h2hZDGk9c2s2kD5P9Ol/OjoIQZqCrmVK42KfStjigaxkN+Cig70D0fV15RFS/O4StNq68AgyhY AGeHWusoqqSIeYBhK9LzdtBKI4HOh5BJ9xwS6qHPzsw8oddjyr6yksFQtCThmsW81P/ZMELlr3h +kD16qDuqG3tozjhPOEes5bxaEjFBrqLvYdSh52p2tD+T7xZRj7ApE8pq6dAilmMOgSlXT9gJ8f cDaLfgAH6yoxYebziACfDMBZBxYr8CzUwpzK4YdQVhcb/JY/MIg5NROO X-Received: by 2002:a05:600c:4fcd:b0:43c:ec0a:ddfd with SMTP id 5b1f17b1804b1-44c91ad6abbmr49054965e9.6.1748188954343; Sun, 25 May 2025 09:02:34 -0700 (PDT) Received: from stoup.. ([195.53.115.74]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-447f73d4a3csm215772545e9.22.2025.05.25.09.02.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 May 2025 09:02:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: edgar.iglesias@gmail.com, philmd@linaro.org Subject: [PATCH v2 06/10] target/microblaze: Use TCGv_i64 for compute_ldst_addr_ea Date: Sun, 25 May 2025 17:02:16 +0100 Message-ID: <20250525160220.222154-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250525160220.222154-1-richard.henderson@linaro.org> References: <20250525160220.222154-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Use an explicit 64-bit type for extended addresses. Signed-off-by: Richard Henderson Reviewed-by: Edgar E. Iglesias --- target/microblaze/translate.c | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index b1fc9e5624..dc597b36e6 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -660,23 +660,23 @@ static TCGv compute_ldst_addr_typeb(DisasContext *dc, int ra, int imm) } #ifndef CONFIG_USER_ONLY -static TCGv compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) +static TCGv_i64 compute_ldst_addr_ea(DisasContext *dc, int ra, int rb) { int addr_size = dc->cfg->addr_size; - TCGv ret = tcg_temp_new(); + TCGv_i64 ret = tcg_temp_new_i64(); if (addr_size == 32 || ra == 0) { if (rb) { - tcg_gen_extu_i32_tl(ret, cpu_R[rb]); + tcg_gen_extu_i32_i64(ret, cpu_R[rb]); } else { - tcg_gen_movi_tl(ret, 0); + return tcg_constant_i64(0); } } else { if (rb) { tcg_gen_concat_i32_i64(ret, cpu_R[rb], cpu_R[ra]); } else { - tcg_gen_extu_i32_tl(ret, cpu_R[ra]); - tcg_gen_shli_tl(ret, ret, 32); + tcg_gen_extu_i32_i64(ret, cpu_R[ra]); + tcg_gen_shli_i64(ret, ret, 32); } if (addr_size < 64) { /* Mask off out of range bits. */ @@ -781,7 +781,7 @@ static bool trans_lbuea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); gen_helper_lbuea(reg_for_write(dc, arg->rd), tcg_env, addr); return true; #endif @@ -813,7 +813,7 @@ static bool trans_lhuea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, false); (mo_endian(dc) == MO_BE ? gen_helper_lhuea_be : gen_helper_lhuea_le) (reg_for_write(dc, arg->rd), tcg_env, addr); @@ -847,7 +847,7 @@ static bool trans_lwea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, false); (mo_endian(dc) == MO_BE ? gen_helper_lwea_be : gen_helper_lwea_le) (reg_for_write(dc, arg->rd), tcg_env, addr); @@ -941,7 +941,7 @@ static bool trans_sbea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); gen_helper_sbea(tcg_env, reg_for_read(dc, arg->rd), addr); return true; #endif @@ -973,7 +973,7 @@ static bool trans_shea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_16, true); (mo_endian(dc) == MO_BE ? gen_helper_shea_be : gen_helper_shea_le) (tcg_env, reg_for_read(dc, arg->rd), addr); @@ -1007,7 +1007,7 @@ static bool trans_swea(DisasContext *dc, arg_typea *arg) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); + TCGv_i64 addr = compute_ldst_addr_ea(dc, arg->ra, arg->rb); gen_alignment_check_ea(dc, addr, arg->rb, arg->rd, MO_32, true); (mo_endian(dc) == MO_BE ? gen_helper_swea_be : gen_helper_swea_le) (tcg_env, reg_for_read(dc, arg->rd), addr);