From patchwork Thu Oct 3 15:55:44 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Newton X-Patchwork-Id: 20789 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-vc0-f199.google.com (mail-vc0-f199.google.com [209.85.220.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 00B9625CAB for ; Thu, 3 Oct 2013 15:55:49 +0000 (UTC) Received: by mail-vc0-f199.google.com with SMTP id lf12sf3689434vcb.6 for ; Thu, 03 Oct 2013 08:55:49 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:message-id:date:from:user-agent :mime-version:to:cc:subject:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe:content-type :content-transfer-encoding; bh=rIC+6oJPfvmc6p0yiHfq5QhhTSclOkQ9P/OVOm5bx6o=; b=Y9W9A2Qo+bqluyHfvoVakTQQYneu1QB5VicGGKQBGGHHdkjA3RjjSbCsRovK0kX6Hk RCnLtJq0D5NaSXcPqeTpZFaBsNT66dmFiOixbvDEwj0EhNi9Ms0lLiJF/3plPIy85E4U yEzklvHBwiiB26hdr9eE5+FgMKsMEKSW8Ihzdcs1MzsmR/QkPia5Dh5wzz3ckbiwDYWn et/AE/vSBaiIL+VASVzd0ZAHq8osbQBoAFjvaq8RuhzHnTVAX9DKlUs4pFM7iV3/wlNY /WeVjg7jSboAB/3JBpc+t/u3NIMqFZt2NhK8VlgUdaGbft22+10k1udA/Q576xHDjZsk bJLg== X-Received: by 10.236.52.7 with SMTP id d7mr7625692yhc.32.1380815749560; Thu, 03 Oct 2013 08:55:49 -0700 (PDT) X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.98.198 with SMTP id ek6ls1079617qeb.45.gmail; Thu, 03 Oct 2013 08:55:49 -0700 (PDT) X-Received: by 10.52.166.200 with SMTP id zi8mr435848vdb.38.1380815749292; Thu, 03 Oct 2013 08:55:49 -0700 (PDT) Received: from mail-ve0-f182.google.com (mail-ve0-f182.google.com [209.85.128.182]) by mx.google.com with ESMTPS id h2si1880095vcy.92.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 03 Oct 2013 08:55:49 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.128.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.182; Received: by mail-ve0-f182.google.com with SMTP id oy12so1909806veb.27 for ; Thu, 03 Oct 2013 08:55:49 -0700 (PDT) X-Gm-Message-State: ALoCoQkJ0RzERvE04YK5GBgfbZZK8jqumYKmT9qj07atJ3Qwm2goa3wQ4MXpTbNg/6SJOoOir8b0 X-Received: by 10.58.168.205 with SMTP id zy13mr8036858veb.19.1380815748985; Thu, 03 Oct 2013 08:55:48 -0700 (PDT) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp189057vcz; Thu, 3 Oct 2013 08:55:48 -0700 (PDT) X-Received: by 10.14.8.72 with SMTP id 48mr13686807eeq.25.1380815747853; Thu, 03 Oct 2013 08:55:47 -0700 (PDT) Received: from mail-ee0-f46.google.com (mail-ee0-f46.google.com [74.125.83.46]) by mx.google.com with ESMTPS id l4si6531612eew.311.1969.12.31.16.00.00 (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 03 Oct 2013 08:55:47 -0700 (PDT) Received-SPF: neutral (google.com: 74.125.83.46 is neither permitted nor denied by best guess record for domain of will.newton@linaro.org) client-ip=74.125.83.46; Received: by mail-ee0-f46.google.com with SMTP id c13so1203690eek.19 for ; Thu, 03 Oct 2013 08:55:47 -0700 (PDT) X-Received: by 10.14.5.3 with SMTP id 3mr5280691eek.49.1380815747123; Thu, 03 Oct 2013 08:55:47 -0700 (PDT) Received: from localhost.localdomain (cpc6-seac21-2-0-cust453.7-2.cable.virginmedia.com. [82.1.113.198]) by mx.google.com with ESMTPSA id r48sm17213070eev.14.1969.12.31.16.00.00 (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 03 Oct 2013 08:55:46 -0700 (PDT) Message-ID: <524D9380.5020702@linaro.org> Date: Thu, 03 Oct 2013 16:55:44 +0100 From: Will Newton User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130805 Thunderbird/17.0.8 MIME-Version: 1.0 To: qemu-devel@nongnu.org CC: patches@linaro.org Subject: [PATCHv4 2/2] target-arm: Implement ARMv8 VSEL instruction. X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: will.newton@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.182 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This adds support for the VSEL floating point selection instruction which was added in ARMv8. Signed-off-by: Will Newton --- target-arm/translate.c | 113 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) Changes in v4: - Fix leak of temporaries - Extend condition values to 64bit in the DP case diff --git a/target-arm/translate.c b/target-arm/translate.c index 2c1458a..db2d862 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2880,6 +2880,119 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) rm = VFP_SREG_M(insn); } + if ((insn & 0x0f800e50) == 0x0e000a00) { + /* vsel */ + uint32_t cc = (insn >> 20) & 3; + + /* ARMv8 VFP. */ + if (!arm_feature(env, ARM_FEATURE_V8)) { + return 1; + } + + if (dp) { + TCGv_i64 ftmp1, ftmp2, ftmp3; + TCGv_i64 tmp, zero, zf, nf, vf; + + zero = tcg_const_i64(0); + + ftmp1 = tcg_temp_new_i64(); + ftmp2 = tcg_temp_new_i64(); + ftmp3 = tcg_temp_new_i64(); + + zf = tcg_temp_new_i64(); + nf = tcg_temp_new_i64(); + vf = tcg_temp_new_i64(); + + tcg_gen_extu_i32_i64(zf, cpu_ZF); + tcg_gen_extu_i32_i64(nf, cpu_NF); + tcg_gen_extu_i32_i64(vf, cpu_VF); + + tcg_gen_ld_f64(ftmp1, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f64(ftmp2, cpu_env, vfp_reg_offset(dp, rm)); + switch (cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i64(TCG_COND_EQ, ftmp3, zf, zero, + ftmp1, ftmp2); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i64(TCG_COND_LT, ftmp3, vf, zero, + ftmp1, ftmp2); + break; + case 2: /* ge: N == V -> N ^ V == 0 */ + tmp = tcg_temp_new_i64(); + tcg_gen_xor_i64(tmp, vf, nf); + tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero, + ftmp1, ftmp2); + tcg_temp_free_i64(tmp); + break; + case 3: /* gt: !Z && N == V */ + tcg_gen_movcond_i64(TCG_COND_NE, ftmp3, zf, zero, + ftmp1, ftmp2); + tmp = tcg_temp_new_i64(); + tcg_gen_xor_i64(tmp, vf, nf); + tcg_gen_movcond_i64(TCG_COND_GE, ftmp3, tmp, zero, + ftmp3, ftmp2); + tcg_temp_free_i64(tmp); + break; + } + tcg_gen_st_f64(ftmp3, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i64(ftmp1); + tcg_temp_free_i64(ftmp2); + tcg_temp_free_i64(ftmp3); + + tcg_temp_free_i64(zf); + tcg_temp_free_i64(nf); + tcg_temp_free_i64(vf); + + tcg_temp_free_i64(zero); + } else { + TCGv_i32 ftmp1, ftmp2, ftmp3; + TCGv_i32 tmp, zero; + + zero = tcg_const_i32(0); + + ftmp1 = tcg_temp_new_i32(); + ftmp2 = tcg_temp_new_i32(); + ftmp3 = tcg_temp_new_i32(); + tcg_gen_ld_f32(ftmp1, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f32(ftmp2, cpu_env, vfp_reg_offset(dp, rm)); + switch (cc) { + case 0: /* eq: Z */ + tcg_gen_movcond_i32(TCG_COND_EQ, ftmp3, cpu_ZF, zero, + ftmp1, ftmp2); + break; + case 1: /* vs: V */ + tcg_gen_movcond_i32(TCG_COND_LT, ftmp3, cpu_VF, zero, + ftmp1, ftmp2); + break; + case 2: /* ge: N == V -> N ^ V == 0 */ + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero, + ftmp1, ftmp2); + tcg_temp_free_i32(tmp); + break; + case 3: /* gt: !Z && N == V */ + tcg_gen_movcond_i32(TCG_COND_NE, ftmp3, cpu_ZF, zero, + ftmp1, ftmp2); + tmp = tcg_temp_new_i32(); + tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); + tcg_gen_movcond_i32(TCG_COND_GE, ftmp3, tmp, zero, + ftmp3, ftmp2); + tcg_temp_free_i32(tmp); + break; + } + tcg_gen_st_f32(ftmp3, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i32(ftmp1); + tcg_temp_free_i32(ftmp2); + tcg_temp_free_i32(ftmp3); + + tcg_temp_free_i32(zero); + } + + return 0; + } + veclen = s->vec_len; if (op == 15 && rn > 3) veclen = 0;