From patchwork Thu Nov 28 17:07:34 2013 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Newton X-Patchwork-Id: 21845 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-ob0-f199.google.com (mail-ob0-f199.google.com [209.85.214.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 3616A20299 for ; Thu, 28 Nov 2013 17:07:39 +0000 (UTC) Received: by mail-ob0-f199.google.com with SMTP id gq1sf28031840obb.2 for ; Thu, 28 Nov 2013 09:07:38 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:message-id:date:from:user-agent :mime-version:to:cc:subject:x-original-sender :x-original-authentication-results:precedence:mailing-list:list-id :list-post:list-help:list-archive:list-unsubscribe:content-type :content-transfer-encoding; bh=dwFGIASBWcf+GMvFxYm15s9lIxbO1iW1CcvkDh3MU0M=; b=NpwMkL811uz12OC26F5Xq6mF64YuaMSdl41nDD1SwLSm1a4HJukFDFmyyATMS/t5YO gwCOAclx9DHbqYFxgFzlube+k8BKbGwv77JSUkDXPmJFgCwGfy5eruh9XsLx4BhzUwPz 1T4TsuNctq/6u0Yk0jJl2R1PDLpgzEE3xryQvi1MtGqpu2GJ9oF1eo1rYBnk05+4RBYu NAGRFLFZkQ2Uz2dXiJ7T9B8tYhs2CdaKgWpVhfKKofX+MnSXZvbyqxjHPmx5QRExwy7A bCQTcQKH6Kw0J5zInsCj2DJhKkZXov/aOIfB1fgQ5YmBAZvz8ZXWgRcYWFJRWm4V4OmQ 7mPw== X-Gm-Message-State: ALoCoQk7EZu8Jkv0J6QI1uiQ5wM591kLTZTXTcGmAt3/ZgIuKUlollC6/ujRuPSl7ZkOoqzg9wX1 X-Received: by 10.50.85.109 with SMTP id g13mr1260467igz.1.1385658458658; Thu, 28 Nov 2013 09:07:38 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.49.4.105 with SMTP id j9ls3690051qej.94.gmail; Thu, 28 Nov 2013 09:07:38 -0800 (PST) X-Received: by 10.58.210.39 with SMTP id mr7mr24041461vec.18.1385658458568; Thu, 28 Nov 2013 09:07:38 -0800 (PST) Received: from mail-vb0-f48.google.com (mail-vb0-f48.google.com [209.85.212.48]) by mx.google.com with ESMTPS id gq10si23182891vdc.30.2013.11.28.09.07.38 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 28 Nov 2013 09:07:38 -0800 (PST) Received-SPF: neutral (google.com: 209.85.212.48 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.212.48; Received: by mail-vb0-f48.google.com with SMTP id x16so5940350vbf.21 for ; Thu, 28 Nov 2013 09:07:38 -0800 (PST) X-Received: by 10.52.118.98 with SMTP id kl2mr11948493vdb.30.1385658458485; Thu, 28 Nov 2013 09:07:38 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patches@linaro.org Received: by 10.220.174.196 with SMTP id u4csp29432vcz; Thu, 28 Nov 2013 09:07:38 -0800 (PST) X-Received: by 10.14.94.197 with SMTP id n45mr1775097eef.65.1385658457508; Thu, 28 Nov 2013 09:07:37 -0800 (PST) Received: from mail-ea0-f172.google.com (mail-ea0-f172.google.com [209.85.215.172]) by mx.google.com with ESMTPS id z8si665307eel.354.2013.11.28.09.07.37 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Thu, 28 Nov 2013 09:07:37 -0800 (PST) Received-SPF: neutral (google.com: 209.85.215.172 is neither permitted nor denied by best guess record for domain of will.newton@linaro.org) client-ip=209.85.215.172; Received: by mail-ea0-f172.google.com with SMTP id q10so6073368ead.3 for ; Thu, 28 Nov 2013 09:07:37 -0800 (PST) X-Received: by 10.15.21.205 with SMTP id d53mr405132eeu.106.1385658457095; Thu, 28 Nov 2013 09:07:37 -0800 (PST) Received: from localhost.localdomain (cpc6-seac21-2-0-cust453.7-2.cable.virginm.net. [82.1.113.198]) by mx.google.com with ESMTPSA id a45sm31796332eem.6.2013.11.28.09.07.35 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 28 Nov 2013 09:07:36 -0800 (PST) Message-ID: <52977856.4060305@linaro.org> Date: Thu, 28 Nov 2013 17:07:34 +0000 From: Will Newton User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.0 MIME-Version: 1.0 To: qemu-devel@nongnu.org CC: Patch Tracking Subject: [PATCH v6 3/4] target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions. X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: will.newton@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.212.48 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , This adds support for the ARMv8 floating point VMAXNM and VMINNM instructions. Signed-off-by: Will Newton --- target-arm/helper.c | 41 +++++++++++++++++++++++++++++++++++++++++ target-arm/helper.h | 5 +++++ target-arm/translate.c | 43 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 89 insertions(+) Changes in v6: - New patch diff --git a/target-arm/helper.c b/target-arm/helper.c index 3445813..e5428d1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4079,3 +4079,44 @@ float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp) float_status *fpst = fpstp; return float64_muladd(a, b, c, 0, fpst); } + +/* ARMv8 VMAXNM/VMINNM */ +float32 VFP_HELPER(maxnm, s)(float32 a, float32 b, void *fpstp) +{ + float_status *fpst = fpstp; + if (float32_is_quiet_nan(a) && !float32_is_quiet_nan(b)) + return b; + else if (float32_is_quiet_nan(b) && !float32_is_quiet_nan(a)) + return a; + return float32_max(a, b, fpst); +} + +float64 VFP_HELPER(maxnm, d)(float64 a, float64 b, void *fpstp) +{ + float_status *fpst = fpstp; + if (float64_is_quiet_nan(a) && !float64_is_quiet_nan(b)) + return b; + else if (float64_is_quiet_nan(b) && !float64_is_quiet_nan(a)) + return a; + return float64_max(a, b, fpst); +} + +float32 VFP_HELPER(minnm, s)(float32 a, float32 b, void *fpstp) +{ + float_status *fpst = fpstp; + if (float32_is_quiet_nan(a) && !float32_is_quiet_nan(b)) + return b; + else if (float32_is_quiet_nan(b) && !float32_is_quiet_nan(a)) + return a; + return float32_min(a, b, fpst); +} + +float64 VFP_HELPER(minnm, d)(float64 a, float64 b, void *fpstp) +{ + float_status *fpst = fpstp; + if (float64_is_quiet_nan(a) && !float64_is_quiet_nan(b)) + return b; + else if (float64_is_quiet_nan(b) && !float64_is_quiet_nan(a)) + return a; + return float64_min(a, b, fpst); +} diff --git a/target-arm/helper.h b/target-arm/helper.h index cac9564..d459a39 100644 --- a/target-arm/helper.h +++ b/target-arm/helper.h @@ -132,6 +132,11 @@ DEF_HELPER_2(neon_fcvt_f32_to_f16, i32, f32, env) DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_maxnmd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_maxnms, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_minnmd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_minnms, f32, f32, f32, ptr) + DEF_HELPER_3(recps_f32, f32, f32, f32, env) DEF_HELPER_3(rsqrts_f32, f32, f32, f32, env) DEF_HELPER_2(recpe_f32, f32, f32, env) diff --git a/target-arm/translate.c b/target-arm/translate.c index 4e7077e..cac7668 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -2738,6 +2738,49 @@ static int disas_vfp_v8_insn(CPUARMState *env, DisasContext *s, uint32_t insn) } return 0; + } else if ((insn & 0x0fb00e10) == 0x0e800a00) { + /* vmaxnm/vminnm */ + uint32_t vmin = (insn >> 6) & 1; + TCGv_ptr fpst; + fpst = get_fpstatus_ptr(0); + if (dp) { + TCGv_i64 ftmp1, ftmp2, ftmp3; + + ftmp1 = tcg_temp_new_i64(); + ftmp2 = tcg_temp_new_i64(); + ftmp3 = tcg_temp_new_i64(); + + tcg_gen_ld_f64(ftmp1, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f64(ftmp2, cpu_env, vfp_reg_offset(dp, rm)); + if (vmin) + gen_helper_vfp_minnmd(ftmp3, ftmp1, ftmp2, fpst); + else + gen_helper_vfp_maxnmd(ftmp3, ftmp1, ftmp2, fpst); + tcg_gen_st_f64(ftmp3, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i64(ftmp1); + tcg_temp_free_i64(ftmp2); + tcg_temp_free_i64(ftmp3); + } else { + TCGv_i32 ftmp1, ftmp2, ftmp3; + + ftmp1 = tcg_temp_new_i32(); + ftmp2 = tcg_temp_new_i32(); + ftmp3 = tcg_temp_new_i32(); + + tcg_gen_ld_f32(ftmp1, cpu_env, vfp_reg_offset(dp, rn)); + tcg_gen_ld_f32(ftmp2, cpu_env, vfp_reg_offset(dp, rm)); + if (vmin) + gen_helper_vfp_minnms(ftmp3, ftmp1, ftmp2, fpst); + else + gen_helper_vfp_maxnms(ftmp3, ftmp1, ftmp2, fpst); + tcg_gen_st_f32(ftmp3, cpu_env, vfp_reg_offset(dp, rd)); + tcg_temp_free_i32(ftmp1); + tcg_temp_free_i32(ftmp2); + tcg_temp_free_i32(ftmp3); + } + + tcg_temp_free_ptr(fpst); + return 0; } return 1; }