[4.9,v3,0/2] arm64: entry: Place an SB sequence following an ERET instruction

Message ID	1598294182-34012-1-git-send-email-f.fainelli@gmail.com
Headers	show Return-Path: <SRS0=P6ku=CC=vger.kernel.org=stable-owner@kernel.org> From: Florian Fainelli <f.fainelli@gmail.com> To: linux-arm-kernel@lists.infradead.org Cc: Florian Fainelli <f.fainelli@gmail.com>, Greg KH <gregkh@linuxfoundation.org>, Will Deacon <will@kernel.org>, stable@vger.kernel.org, Catalin Marinas <catalin.marinas@arm.com>, Marc Zyngier <maz@kernel.org>, James Morse <james.morse@arm.com>, Julien Thierry <julien.thierry.kdev@gmail.com>, Suzuki K Poulose <suzuki.poulose@arm.com>, Mark Rutland <mark.rutland@arm.com>, Mark Brown <broonie@kernel.org>, Kristina Martsenko <kristina.martsenko@arm.com>, Sami Tolvanen <samitolvanen@google.com>, Andrew Jones <drjones@redhat.com>, Ard Biesheuvel <ardb@kernel.org>, Nick Desaulniers <ndesaulniers@google.com>, Fangrui Song <maskray@google.com>, open list <linux-kernel@vger.kernel.org>, "open list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)" <kvmarm@lists.cs.columbia.edu> Subject: [PATCH stable 4.9 v3 0/2] arm64: entry: Place an SB sequence following an ERET instruction Date: Mon, 24 Aug 2020 11:36:20 -0700 Message-Id: <1598294182-34012-1-git-send-email-f.fainelli@gmail.com> Sender: stable-owner@vger.kernel.org Precedence: bulk
Series	arm64: entry: Place an SB sequence following an ERET instruction \| expand [4.9,v3,0/2] arm64: entry: Place an SB sequence following an ERET instruction [4.9,v3,1/2] arm64: Add support for SB barrier and patch in over DSB; ISB sequences [4.9,v3,2/2] arm64: entry: Place an SB sequence following an ERET instruction

Message ID

1598294182-34012-1-git-send-email-f.fainelli@gmail.com

Headers

From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Florian Fainelli <f.fainelli@gmail.com>,
	Greg KH <gregkh@linuxfoundation.org>,
	Will Deacon <will@kernel.org>, stable@vger.kernel.org,
	Catalin Marinas <catalin.marinas@arm.com>, Marc Zyngier <maz@kernel.org>,
	James Morse <james.morse@arm.com>,
	Julien Thierry <julien.thierry.kdev@gmail.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mark Rutland <mark.rutland@arm.com>, Mark Brown <broonie@kernel.org>,
	Kristina Martsenko <kristina.martsenko@arm.com>,
	Sami Tolvanen <samitolvanen@google.com>,
	Andrew Jones <drjones@redhat.com>, Ard Biesheuvel <ardb@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	Fangrui Song <maskray@google.com>,
	open list <linux-kernel@vger.kernel.org>,
	"open list:KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64)" 
	<kvmarm@lists.cs.columbia.edu>
Subject: [PATCH stable 4.9 v3 0/2] arm64: entry: Place an SB sequence
	following an ERET instruction
Date: Mon, 24 Aug 2020 11:36:20 -0700
Message-Id: <1598294182-34012-1-git-send-email-f.fainelli@gmail.com>
Sender: stable-owner@vger.kernel.org
Precedence: bulk

Series

arm64: entry: Place an SB sequence following an ERET instruction | expand

Message

Florian Fainelli Aug. 24, 2020, 6:36 p.m. UTC

Changes in v3:

- included missing preliminary patch to define the SB barrier instruction, see
  patch change log for details on how it was back ported into v4.9

Changes in v2:

- added missing hunk in hyp/entry.S per Will's feedback

Will Deacon (2):
  arm64: Add support for SB barrier and patch in over DSB; ISB sequences
  arm64: entry: Place an SB sequence following an ERET instruction

 arch/arm64/include/asm/assembler.h  | 13 +++++++++++++
 arch/arm64/include/asm/barrier.h    |  4 ++++
 arch/arm64/include/asm/cpucaps.h    |  3 ++-
 arch/arm64/include/asm/sysreg.h     | 13 +++++++++++++
 arch/arm64/include/asm/uaccess.h    |  3 +--
 arch/arm64/include/uapi/asm/hwcap.h |  1 +
 arch/arm64/kernel/cpufeature.c      | 22 +++++++++++++++++++++-
 arch/arm64/kernel/cpuinfo.c         |  1 +
 arch/arm64/kernel/entry.S           |  2 ++
 arch/arm64/kvm/hyp/entry.S          |  2 ++
 arch/arm64/kvm/hyp/hyp-entry.S      |  4 ++++
 11 files changed, 64 insertions(+), 4 deletions(-)