[4.14,067/119] arm64: Get rid of __smccc_workaround_1_hvc_*

Message ID	20191027203333.787221281@linuxfoundation.org
State	New
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; From: Greg Kroah-Hartman <gregkh@linuxfoundation.org> To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>, Marc Zyngier <marc.zyngier@arm.com>, Will Deacon <will.deacon@arm.com>, Ard Biesheuvel <ard.biesheuvel@linaro.org> Subject: [PATCH 4.14 067/119] arm64: Get rid of __smccc_workaround_1_hvc_* Date: Sun, 27 Oct 2019 22:00:44 +0100 Message-Id: <20191027203333.787221281@linuxfoundation.org> In-Reply-To: <20191027203259.948006506@linuxfoundation.org> References: <20191027203259.948006506@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: stable-owner@vger.kernel.org Precedence: bulk
Series	None \| expand [4.14,039/119] arm64: Fix the feature type for ID register fields [4.14,041/119] arm64: Documentation: cpu-feature-registers: Remove RES0 fields [4.14,048/119] arm64: capabilities: Move errata processing code [4.14,050/119] arm64: capabilities: Add flags to handle the conflicts on late CPU [4.14,051/119] arm64: capabilities: Unify the verification [4.14,060/119] arm64: capabilities: Change scope of VHE to Boot CPU feature [4.14,063/119] arm64: Add MIDR encoding for Arm Cortex-A55 and Cortex-A35 [4.14,067/119] arm64: Get rid of __smccc_workaround_1_hvc_* [4.14,068/119] arm64: cpufeature: Detect SSBS and advertise to userspace [4.14,069/119] arm64: ssbd: Add support for PSTATE.SSBS rather than trapping to EL3 [4.14,073/119] arm64: add sysfs vulnerability show for meltdown [4.14,076/119] arm64: Provide a command line to disable spectre_v2 mitigation [4.14,082/119] arm64: Force SSBS on context switch [4.14,083/119] arm64: Use firmware to detect CPUs that are not affected by Spectre-v2

Message ID

20191027203333.787221281@linuxfoundation.org

State

New

Headers

Received-SPF: pass (google.com: best guess record for domain of
	stable-owner@vger.kernel.org designates 209.132.180.67 as
	permitted sender) client-ip=209.132.180.67; 
From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org, stable@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
	Marc Zyngier <marc.zyngier@arm.com>, Will Deacon <will.deacon@arm.com>,
	Ard Biesheuvel <ard.biesheuvel@linaro.org>
Subject: [PATCH 4.14 067/119] arm64: Get rid of __smccc_workaround_1_hvc_*
Date: Sun, 27 Oct 2019 22:00:44 +0100
Message-Id: <20191027203333.787221281@linuxfoundation.org>
In-Reply-To: <20191027203259.948006506@linuxfoundation.org>
References: <20191027203259.948006506@linuxfoundation.org>
User-Agent: quilt/0.66
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Series

None | expand

Commit Message

Greg KH Oct. 27, 2019, 9 p.m. UTC

From: Marc Zyngier <marc.zyngier@arm.com>


[ Upstream commit 22765f30dbaf1118c6ff0fcb8b99c9f2b4d396d5 ]

The very existence of __smccc_workaround_1_hvc_* is a thinko, as
KVM will never use a HVC call to perform the branch prediction
invalidation. Even as a nested hypervisor, it would use an SMC
instruction.

Let's get rid of it.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>

Signed-off-by: Will Deacon <will.deacon@arm.com>

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

---
 arch/arm64/kernel/bpi.S        |   12 ++----------
 arch/arm64/kernel/cpu_errata.c |    9 +++------
 2 files changed, 5 insertions(+), 16 deletions(-)

--- a/arch/arm64/kernel/bpi.S
+++ b/arch/arm64/kernel/bpi.S
@@ -56,21 +56,13 @@  ENTRY(__bp_harden_hyp_vecs_start)
 ENTRY(__bp_harden_hyp_vecs_end)
 
 
-.macro smccc_workaround_1 inst
+ENTRY(__smccc_workaround_1_smc_start)
 	sub	sp, sp, #(8 * 4)
 	stp	x2, x3, [sp, #(8 * 0)]
 	stp	x0, x1, [sp, #(8 * 2)]
 	mov	w0, #ARM_SMCCC_ARCH_WORKAROUND_1
-	\inst	#0
+	smc	#0
 	ldp	x2, x3, [sp, #(8 * 0)]
 	ldp	x0, x1, [sp, #(8 * 2)]
 	add	sp, sp, #(8 * 4)
-.endm
-
-ENTRY(__smccc_workaround_1_smc_start)
-	smccc_workaround_1	smc
 ENTRY(__smccc_workaround_1_smc_end)
-
-ENTRY(__smccc_workaround_1_hvc_start)
-	smccc_workaround_1	hvc
-ENTRY(__smccc_workaround_1_hvc_end)
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -85,8 +85,6 @@  DEFINE_PER_CPU_READ_MOSTLY(struct bp_har
 #ifdef CONFIG_KVM
 extern char __smccc_workaround_1_smc_start[];
 extern char __smccc_workaround_1_smc_end[];
-extern char __smccc_workaround_1_hvc_start[];
-extern char __smccc_workaround_1_hvc_end[];
 
 static void __copy_hyp_vect_bpi(int slot, const char *hyp_vecs_start,
 				const char *hyp_vecs_end)
@@ -131,8 +129,6 @@  static void __install_bp_hardening_cb(bp
 #else
 #define __smccc_workaround_1_smc_start		NULL
 #define __smccc_workaround_1_smc_end		NULL
-#define __smccc_workaround_1_hvc_start		NULL
-#define __smccc_workaround_1_hvc_end		NULL
 
 static void __install_bp_hardening_cb(bp_hardening_cb_t fn,
 				      const char *hyp_vecs_start,
@@ -206,8 +202,9 @@  enable_smccc_arch_workaround_1(const str
 		if ((int)res.a0 < 0)
 			return;
 		cb = call_hvc_arch_workaround_1;
-		smccc_start = __smccc_workaround_1_hvc_start;
-		smccc_end = __smccc_workaround_1_hvc_end;
+		/* This is a guest, no need to patch KVM vectors */
+		smccc_start = NULL;
+		smccc_end = NULL;
 		break;
 
 	case PSCI_CONDUIT_SMC:

[4.14,067/119] arm64: Get rid of __smccc_workaround_1_hvc_*

Commit Message

Patch