From patchwork Thu Aug 20 09:20:11 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Greg KH X-Patchwork-Id: 265300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH, MAILING_LIST_MULTI, SIGNED_OFF_BY, SPF_HELO_NONE, SPF_PASS, URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA755C433DF for ; Thu, 20 Aug 2020 13:32:15 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A3DEC208C7 for ; Thu, 20 Aug 2020 13:32:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597930335; bh=YoX+O+1UOgcVdZatpKv5LLn+ibV711RniuxfJZfW09Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=S1qd9nuREbUKsnv82qqZE8Ou9xIsivo7L/PXSsIDaGVV+zCSpwfQVzgeWRLtNlVOv PbA9pDsKWN7HKH/gs9iSLZeU2Ig5AlPGZtrUb/Hm78EJVgM8Gsr+f2W1Xr/kNOD9Fp z9kqkGDpTDcnyBI8OErkAvRAs2FX9VBOeWvdPaP4= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729388AbgHTNbn (ORCPT ); Thu, 20 Aug 2020 09:31:43 -0400 Received: from mail.kernel.org ([198.145.29.99]:44870 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728125AbgHTJc0 (ORCPT ); Thu, 20 Aug 2020 05:32:26 -0400 Received: from localhost (83-86-89-107.cable.dynamic.v4.ziggo.nl [83.86.89.107]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 4E17722BEB; Thu, 20 Aug 2020 09:32:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1597915945; bh=YoX+O+1UOgcVdZatpKv5LLn+ibV711RniuxfJZfW09Y=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VDFRm59mxnOyy/Qsqosw1zGlOkKWy2Nbf5NDQeko/U4NwH1VLOIyQNoxDZwiOk5pZ A73dW/C5RwyxAzLzbew/mYYhzaZOXYT+hNJ4PlQ/CuiuiFk8sUSlRE+W8RsQVAHWKd 0mbwhKJMXrFAZ37ZUga7AL6RwMgZtAXhPAo4vAi4= From: Greg Kroah-Hartman To: linux-kernel@vger.kernel.org Cc: Greg Kroah-Hartman , stable@vger.kernel.org, Jacob Pan , Lu Baolu , Eric Auger , Joerg Roedel , Sasha Levin Subject: [PATCH 5.8 160/232] iommu/vt-d: Warn on out-of-range invalidation address Date: Thu, 20 Aug 2020 11:20:11 +0200 Message-Id: <20200820091620.562216591@linuxfoundation.org> X-Mailer: git-send-email 2.28.0 In-Reply-To: <20200820091612.692383444@linuxfoundation.org> References: <20200820091612.692383444@linuxfoundation.org> User-Agent: quilt/0.66 MIME-Version: 1.0 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org From: Jacob Pan [ Upstream commit 1ff00279655d95ae9c285c39878aedf9ff008d25 ] For guest requested IOTLB invalidation, address and mask are provided as part of the invalidation data. VT-d HW silently ignores any address bits below the mask. SW shall also allow such case but give warning if address does not align with the mask. This patch relax the fault handling from error to warning and proceed with invalidation request with the given mask. Fixes: 6ee1b77ba3ac0 ("iommu/vt-d: Add svm/sva invalidate function") Signed-off-by: Jacob Pan Signed-off-by: Lu Baolu Reviewed-by: Eric Auger Link: https://lore.kernel.org/r/20200724014925.15523-7-baolu.lu@linux.intel.com Signed-off-by: Joerg Roedel Signed-off-by: Sasha Levin --- drivers/iommu/intel/iommu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/intel/iommu.c b/drivers/iommu/intel/iommu.c index e7bce09a9f735..04e82f1756010 100644 --- a/drivers/iommu/intel/iommu.c +++ b/drivers/iommu/intel/iommu.c @@ -5452,13 +5452,12 @@ intel_iommu_sva_invalidate(struct iommu_domain *domain, struct device *dev, switch (BIT(cache_type)) { case IOMMU_CACHE_INV_TYPE_IOTLB: + /* HW will ignore LSB bits based on address mask */ if (inv_info->granularity == IOMMU_INV_GRANU_ADDR && size && (inv_info->addr_info.addr & ((BIT(VTD_PAGE_SHIFT + size)) - 1))) { - pr_err_ratelimited("Address out of range, 0x%llx, size order %llu\n", + pr_err_ratelimited("User address not aligned, 0x%llx, size order %llu\n", inv_info->addr_info.addr, size); - ret = -ERANGE; - goto out_unlock; } /*