| Message ID | 20200218083503.5468-1-patrick.delaunay@st.com |
|---|---|
| Headers | show |
| Series | usb: host: dwc2: use driver model for PHY and CLOCK | expand |
On 2/18/20 9:34 AM, Patrick Delaunay wrote: > > In this serie I update the DWC2 host driver to use the device tree > information and the associated PHY and CLOCK drivers when they are > availables. > > The V4 is rebased on latest master (v2020.04-rc2). > CI-Tavis build is OK: > https://travis-ci.org/patrickdelaunay/u-boot/builds/651479714 > > NB: CI-Travis build was OK for all target after V3: > https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 > As in V2, I cause the warnings for some boards: > drivers/usb/host/built-in.o: In function `dwc2_usb_remove': > drivers/usb/host/dwc2.c:1441: undefined reference to `clk_disable_bulk' > > I test this serie on stm32mp157c-ev1 board, with PHY and CLK > support > > The U-CLASS are provided by: > - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c > - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c > - RESET by RCC reset driver = drivers/reset/stm32-reset.c > > And I activate the configuration > +CONFIG_USB_DWC2=y Simon, can you test this on SOCFPGA ? [...]
On Tue, Feb 18, 2020 at 6:53 PM Marek Vasut <marex at denx.de> wrote: > > On 2/18/20 9:34 AM, Patrick Delaunay wrote: > > > > In this serie I update the DWC2 host driver to use the device tree > > information and the associated PHY and CLOCK drivers when they are > > availables. > > > > The V4 is rebased on latest master (v2020.04-rc2). > > CI-Tavis build is OK: > > https://travis-ci.org/patrickdelaunay/u-boot/builds/651479714 > > > > NB: CI-Travis build was OK for all target after V3: > > https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 > > As in V2, I cause the warnings for some boards: > > drivers/usb/host/built-in.o: In function `dwc2_usb_remove': > > drivers/usb/host/dwc2.c:1441: undefined reference to `clk_disable_bulk' > > > > I test this serie on stm32mp157c-ev1 board, with PHY and CLK > > support > > > > The U-CLASS are provided by: > > - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c > > - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c > > - RESET by RCC reset driver = drivers/reset/stm32-reset.c > > > > And I activate the configuration > > +CONFIG_USB_DWC2=y > > Simon, can you test this on SOCFPGA ? I can test if it probes, but I don't have anything running on that USB port the socfpga_socrates board has. Would that be enought to test? Regards, Simon > > [...]
Am 19.02.2020 um 08:27 schrieb Simon Goldschmidt: > On Tue, Feb 18, 2020 at 6:53 PM Marek Vasut <marex at denx.de> wrote: >> >> On 2/18/20 9:34 AM, Patrick Delaunay wrote: >>> >>> In this serie I update the DWC2 host driver to use the device tree >>> information and the associated PHY and CLOCK drivers when they are >>> availables. >>> >>> The V4 is rebased on latest master (v2020.04-rc2). >>> CI-Tavis build is OK: >>> https://travis-ci.org/patrickdelaunay/u-boot/builds/651479714 >>> >>> NB: CI-Travis build was OK for all target after V3: >>> https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 >>> As in V2, I cause the warnings for some boards: >>> drivers/usb/host/built-in.o: In function `dwc2_usb_remove': >>> drivers/usb/host/dwc2.c:1441: undefined reference to `clk_disable_bulk' >>> >>> I test this serie on stm32mp157c-ev1 board, with PHY and CLK >>> support >>> >>> The U-CLASS are provided by: >>> - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c >>> - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c >>> - RESET by RCC reset driver = drivers/reset/stm32-reset.c >>> >>> And I activate the configuration >>> +CONFIG_USB_DWC2=y >> >> Simon, can you test this on SOCFPGA ? > > I can test if it probes, but I don't have anything running on that USB port > the socfpga_socrates board has. Would that be enought to test? Tested the whole series on socfpga_socrates by instantiating the driver. Shows the same behaviour as before (I still have no OTG cable to test attaching a storage device). Regards, Simon > > Regards, > Simon > >> >> [...]
In this serie I update the DWC2 host driver to use the device tree information and the associated PHY and CLOCK drivers when they are availables. The V4 is rebased on latest master (v2020.04-rc2). CI-Tavis build is OK: https://travis-ci.org/patrickdelaunay/u-boot/builds/651479714 NB: CI-Travis build was OK for all target after V3: https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 As in V2, I cause the warnings for some boards: drivers/usb/host/built-in.o: In function `dwc2_usb_remove': drivers/usb/host/dwc2.c:1441: undefined reference to `clk_disable_bulk' I test this serie on stm32mp157c-ev1 board, with PHY and CLK support The U-CLASS are provided by: - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c - RESET by RCC reset driver = drivers/reset/stm32-reset.c And I activate the configuration +CONFIG_USB_DWC2=y PS: it is not the default configuration to avoid conflict with gadget driver To solve a binding issue, I also deactivate the gadget support: by default only one driver is bound to the usbotg_hs node with "snps,dwc2" compatible, and today it is the device one (the first in the driver list). I also need to deactivate hnp-srp support with: &usbotg_hs { /* need to disable ONLY for HOST support */ hnp-srp-disable; }; WARNING: OTG with device or host support is not correctly handle by DWC2 driver (see example for dynamic OTG role in DWC3 driver). The tests executed on the stm32mp157c-ev1 target: STM32MP> usb start starting USB... Bus usb-otg at 49000000: USB DWC2 Bus usbh-ehci at 5800d000: USB EHCI 1.00 scanning bus usb-otg at 49000000 for devices... 2 USB Device(s) found scanning bus usbh-ehci at 5800d000 for devices... 3 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found STM32MP> usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Mass Storage (480 Mb/s, 300mA) Verbatim STORE N GO 070731C8ACD7EE97 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (480 Mb/s, 2mA) STM32MP> ls usb 0 <DIR> 4096 . <DIR> 4096 .. <DIR> 16384 lost+found <DIR> 4096 record 1490212 xipImage 21058006 vmlinux STM32MP> load usb 0 0xC0000000 vmlinux 21058006 bytes read in 10851 ms (1.9 MiB/s) Changes in v4: - Add stub for all functions using 'struct clk' or 'struct clk_bulk' after remarks on v3 Changes in v3: - Add stub for clk_disable_bulk Changes in v2: - update dev_err - update commit message - change dev_err to dev_dbg for PHY function call - treat dwc2_shutdown_phy error - add clk_disable_bulk in dwc2_usb_remove Patrick Delaunay (5): dm: clk: add stub when CONFIG_CLK is desactivated usb: host: dwc2: add phy support usb: host: dwc2: add clk support usb: host: dwc2: force reset assert usb: host: dwc2: add trace to have clean usb start drivers/usb/host/dwc2.c | 100 ++++++++++++++++++++++++++++++++++++++- include/clk.h | 101 ++++++++++++++++++++++++++++++++++------ 2 files changed, 187 insertions(+), 14 deletions(-)