diff --git a/arch/arm/cpu/armv7/u8500/Makefile b/arch/arm/cpu/armv7/u8500/Makefile
new file mode 100644
index 0000000..270aa40
--- /dev/null
+++ b/arch/arm/cpu/armv7/u8500/Makefile
@@ -0,0 +1,46 @@
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	= timer.o clock.o
+SOBJS	= lowlevel.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/u8500/clock.c b/arch/arm/cpu/armv7/u8500/clock.c
new file mode 100644
index 0000000..9e3b873
--- /dev/null
+++ b/arch/arm/cpu/armv7/u8500/clock.c
@@ -0,0 +1,56 @@
+/*
+ * (C) Copyright 2009 ST-Ericsson
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct clkrst {
+	unsigned int pcken;
+	unsigned int pckdis;
+	unsigned int kcken;
+	unsigned int kckdis;
+};
+
+static unsigned int clkrst_base[] = {
+	U8500_CLKRST1_BASE,
+	U8500_CLKRST2_BASE,
+	U8500_CLKRST3_BASE,
+	0,
+	U8500_CLKRST5_BASE,
+	U8500_CLKRST6_BASE,
+	U8500_CLKRST7_BASE,	/* ED only */
+};
+
+/* Turn on peripheral clock at PRCC level */
+void u8500_clock_enable(int periph, int cluster, int kern)
+{
+	struct clkrst *clkrst = (struct clkrst *) clkrst_base[periph - 1];
+
+	if (kern != -1)
+		writel(1 << kern, &clkrst->kcken);
+
+	if (cluster != -1)
+		writel(1 << cluster, &clkrst->pcken);
+}
diff --git a/arch/arm/cpu/armv7/u8500/lowlevel.S b/arch/arm/cpu/armv7/u8500/lowlevel.S
new file mode 100644
index 0000000..0e3f8fc
--- /dev/null
+++ b/arch/arm/cpu/armv7/u8500/lowlevel.S
@@ -0,0 +1,33 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <config.h>
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	pc, lr
+
+	.align	5
+.globl reset_cpu
+reset_cpu:
+        ldr r0, =CFG_PRCMU_BASE
+        ldr r1, =0x1
+        str r1, [r0, #0x228]
+_loop_forever:
+	b	_loop_forever
diff --git a/arch/arm/cpu/armv7/u8500/timer.c b/arch/arm/cpu/armv7/u8500/timer.c
new file mode 100644
index 0000000..8850fd5
--- /dev/null
+++ b/arch/arm/cpu/armv7/u8500/timer.c
@@ -0,0 +1,167 @@
+/*
+ * Copyright (C) 2010 Linaro Limited
+ * John Rigby <john.rigby@linaro.org>
+ *
+ * Based on original from Linux kernel source and
+ * internal ST-Ericsson U-Boot source.
+ * (C) Copyright 2009 Alessandro Rubini
+ * (C) Copyright 2010 ST-Ericsson
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/hardware.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * The MTU device has some interrupt control registers
+ * followed by 4 timers.
+ */
+
+/* The timers */
+struct u8500_mtu_timer {
+	u32 lr;			/* Load value */
+	u32 cv;			/* Current value */
+	u32 cr;			/* Control reg */
+	u32 bglr;		/* ??? */
+};
+
+/* The MTU that contains the timers */
+struct u8500_mtu {
+	u32 imsc;		/* Interrupt mask set/clear */
+	u32 ris;		/* Raw interrupt status */
+	u32 mis;		/* Masked interrupt status */
+	u32 icr;		/* Interrupt clear register */
+	struct u8500_mtu_timer pt[4];
+};
+
+/* bits for the control register */
+#define MTU_CR_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR */
+#define MTU_CR_32BITS		0x02
+
+#define MTU_CR_PRESCALE_1	0x00
+#define MTU_CR_PRESCALE_16	0x04
+#define MTU_CR_PRESCALE_256	0x08
+#define MTU_CR_PRESCALE_MASK	0x0c
+
+#define MTU_CR_PERIODIC		0x40	/* if 0 = free-running */
+#define MTU_CR_ENA		0x80
+
+/*
+ * The MTU is clocked at 133 MHz by default. (V1 and later)
+ */
+#define TIMER_CLOCK		(133 * 1000 * 1000 / 16)
+#define COUNT_TO_USEC(x)	((x) * 16 / 133)
+#define USEC_TO_COUNT(x)	((x) * 133 / 16)
+#define TICKS_PER_HZ		(TIMER_CLOCK / CONFIG_SYS_HZ)
+#define TICKS_TO_HZ(x)		((x) / TICKS_PER_HZ)
+#define TIMER_LOAD_VAL		0xffffffff
+
+/*
+ * MTU timer to use (from 0 to 3).
+ * Linux ux500 timer0 on MTU0 and timer0 on MTU1
+ */
+#define MTU_TIMER 2
+
+static struct u8500_mtu_timer *timer_base =
+	&((struct u8500_mtu *)U8500_MTU0_BASE_V1)->pt[MTU_TIMER];
+
+/* macro to read the 32 bit timer: since it decrements, we invert read value */
+#define READ_TIMER() (~readl(&timer_base->cv))
+
+/* Configure a free-running, auto-wrap counter with /16 prescaler */
+int timer_init(void)
+{
+	writel(MTU_CR_ENA | MTU_CR_PRESCALE_16 | MTU_CR_32BITS,
+	       &timer_base->cr);
+	reset_timer();
+	return 0;
+}
+
+ulong get_timer_masked(void)
+{
+	/* current tick value */
+	ulong now = TICKS_TO_HZ(READ_TIMER());
+
+	if (now >= gd->lastinc)	/* normal (non rollover) */
+		gd->tbl += (now - gd->lastinc);
+	else			/* rollover */
+		gd->tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) - gd->lastinc) + now;
+	gd->lastinc = now;
+	return gd->tbl;
+}
+
+/* Delay x useconds */
+void __udelay(ulong usec)
+{
+	long tmo = usec * (TIMER_CLOCK / 1000) / 1000;
+	ulong now, last = READ_TIMER();
+
+	while (tmo > 0) {
+		now = READ_TIMER();
+		if (now > last)	/* normal (non rollover) */
+			tmo -= now - last;
+		else		/* rollover */
+			tmo -= TIMER_LOAD_VAL - last + now;
+		last = now;
+	}
+}
+
+ulong get_timer(ulong base)
+{
+	return get_timer_masked() - base;
+}
+
+void set_timer(ulong t)
+{
+	gd->tbl = t;
+}
+
+void reset_timer_masked(void)
+{
+	gd->lastinc = TICKS_TO_HZ(READ_TIMER());
+	gd->tbl = 0;		/* reset ticks to 0 */
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+/*
+ * Emulation of Power architecture long long timebase.
+ *
+ * TODO: Support gd->tbu for real long long timebase.
+ */
+unsigned long long get_ticks(void)
+{
+	return get_timer(0);
+}
+
+/*
+ * Emulation of Power architecture timebase.
+ * NB: Low resolution compared to Power tbclk.
+ */
+ulong get_tbclk(void)
+{
+	return CONFIG_SYS_HZ;
+}
diff --git a/arch/arm/include/asm/arch-u8500/ab8500.h b/arch/arm/include/asm/arch-u8500/ab8500.h
new file mode 100644
index 0000000..02a3c97
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/ab8500.h
@@ -0,0 +1,523 @@
+/*
+ * Copyright (C) ST-Ericsson 2009.
+ *
+ * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _AB8500_H
+#define _AB8500_H
+
+/*
+ * AB8500 bank addresses
+ */
+#define AB8500_SYS_CTRL1_BLOCK	0x1
+#define AB8500_SYS_CTRL2_BLOCK	0x2
+#define AB8500_REGU_CTRL1	0x3
+#define AB8500_REGU_CTRL2	0x4
+#define AB8500_USB		0x5
+#define AB8500_TVOUT		0x6
+#define AB8500_DBI		0x7
+#define AB8500_ECI_AV_ACC	0x8
+#define AB8500_RESERVED	0x9
+#define STw4550_GPADC		0xA
+#define AB8500_GPADC		0xA
+#define AB8500_CHARGER		0xB
+#define AB8500_GAS_GAUGE	0xC
+#define AB8500_AUDIO		0xD
+#define AB8500_INTERRUPT	0xE
+#define AB8500_RTC		0xF
+#define AB8500_MISC		0x10
+#define AB8500_DEBUG		0x12
+#define AB8500_PROD_TEST	0x13
+#define AB8500_OTP_EMUL	0x15
+
+/*
+ * System control 1 register offsets.
+ * Bank = 0x01
+ */
+#define AB8500_TURNON_STAT_REG		0x0100
+#define AB8500_RESET_STAT_REG		0x0101
+#define AB8500_PONKEY1_PRESS_STAT_REG	0x0102
+
+#define AB8500_FSM_STAT1_REG		0x0140
+#define AB8500_FSM_STAT2_REG		0x0141
+#define AB8500_SYSCLK_REQ_STAT_REG	0x0142
+#define AB8500_USB_STAT1_REG		0x0143
+#define AB8500_USB_STAT2_REG		0x0144
+#define AB8500_STATUS_SPARE1_REG	0x0145
+#define AB8500_STATUS_SPARE2_REG	0x0146
+
+#define AB8500_CTRL1_REG		0x0180
+#define AB8500_CTRL2_REG		0x0181
+
+/*
+ * System control 2 register offsets.
+ * bank = 0x02
+ */
+#define AB8500_CTRL3_REG		0x0200
+#define AB8500_CTRL3_RST_DENC_MASK     0x4
+#define AB8500_CTRL3_RST_DENC_SHIFT    2
+#define AB8500_CTRL3_RST_AUD_MASK      0x2
+#define AB8500_CTRL3_RST_AUD_SHIFT     1
+#define AB8500_MAIN_WDOG_CTRL_REG	0x0201
+#define AB8500_MAIN_WDOG_TIMER_REG	0x0202
+#define AB8500_LOW_BAT_REG		0x0203
+#define AB8500_BATT_OK_REG		0x0204
+#define AB8500_SYSCLK_TIMER_REG		0x0205
+#define AB8500_SMPSCLK_CTRL_REG		0x0206
+#define AB8500_SMPSCLK_SEL1_REG		0x0207
+#define AB8500_SMPSCLK_SEL2_REG		0x0208
+#define AB8500_SMPSCLK_SEL3_REG		0x0209
+#define AB8500_SYSULPCLK_CONF_REG	0x020A
+#define AB8500_SYSULPCLK_CTRL1_REG	0x020B
+#define AB8500_SYSCLK_CTRL_REG		0x020C
+#define AB8500_SYSCLK_REQ1_VALID_REG	0x020D
+#define AB8500_SYSCLK_REQ_VALID_REG	0x020E
+#define AB8500_SYSCTRL_SPARE_REG	0x020F
+#define AB8500_PAD_CONF_REG		0x0210
+
+/*
+ * Regu control1 register offsets (SPI)
+ * Bank = 0x03
+ */
+#define AB8500_REGU_SERIAL_CTRL1_REG	0x0300
+#define AB8500_REGU_SERIAL_CTRL2_REG	0x0301
+#define AB8500_REGU_SERIAL_CTRL3_REG	0x0302
+#define AB8500_REGU_REQ_CTRL1_REG	0x0303
+#define AB8500_REGU_REQ_CTRL2_REG	0x0304
+#define AB8500_REGU_REQ_CTRL3_REG	0x0305
+#define AB8500_REGU_REQ_CTRL4_REG	0x0306
+#define AB8500_REGU_SYSCLK_REQ1HP_VALID1_REG	0x0307
+#define AB8500_REGU_SYSCLK_REQ1HP_VALID2_REG	0x0308
+#define AB8500_REGU_HWHPREQ1_VALID1_REG	0x0309
+#define AB8500_REGU_HWHPREQ1_VALID2_REG	0x030A
+#define AB8500_REGU_HWHPREQ2_VALID1_REG	0x030B
+#define AB8500_REGU_HWHPREQ2_VALID2_REG	0x030C
+#define AB8500_REGU_SWHPREQ_VALID1_REG	0x030D
+#define AB8500_REGU_SWHPREQ_VALID2_REG	0x030E
+
+#define AB8500_REGU_SYSCLK_REQ1_VALID_REG	0x030F /* only for ED*/
+#define AB8500_REGU_SYSCLK_REQ2_VALID_REG	0x0310	/*only for ED*/
+
+#define AB8500_REGU_MISC1_REG		0x0380
+#define AB8500_REGU_OTGSUPPLY_CTRL_REG	0x0381
+#define AB8500_REGU_VUSB_CTRL_REG	0x0382 /* see reg manaul*/
+#define AB8500_REGU_VAUDIO_SUPPLY_REG	0x0383
+#define AB8500_REGU_CTRL1_SPARE_REG	0x0384
+
+ /*
+ * Regu control2 register offsets (SPI/APE I2C)
+ * Bank = 0x04
+ */
+#define AB8500_REGU_ARM_REGU1_REG	0x0400
+#define AB8500_REGU_ARM_REGU2_REG	0x0401
+#define AB8500_REGU_VAPE_REGU_REG	0x0402
+#define AB8500_REGU_VSMPS1_REGU_REG	0x0403
+#define AB8500_REGU_VSMPS2_REGU_REG	0x0404
+#define AB8500_REGU_VSMPS3_REGU_REG	0x0405
+#define AB8500_REGU_VPLLVANA_REGU_REG	0x0406
+#define AB8500_REGU_VREF_DDR_REG	0x0407
+#define AB8500_REGU_EXTSUPPLY_REGU_REG	0x0408
+#define AB8500_REGU_VAUX12_REGU_REG	0x0409
+#define AB8500_REGU_VAUX12_REGU_VAUX1_MASK     0x3
+#define AB8500_REGU_VAUX12_REGU_VAUX1_SHIFT    0
+#define AB8500_REGU_VAUX12_REGU_VAUX1_FORCE_HP 0x1
+#define AB8500_REGU_VRF1VAUX3_REGU_REG	0x040A
+#define AB8500_REGU_VARM_SEL1_REG	0x040B
+#define AB8500_REGU_VARM_SEL2_REG	0x040C
+#define AB8500_REGU_VARM_SEL3_REG	0x040D
+#define AB8500_REGU_VAPE_SEL1_REG	0x040E
+#define AB8500_REGU_VAPE_SEL2_REG	0x040F
+#define AB8500_REGU_VAPE_SEL3_REG	0x0410
+#define AB8500_REGU_VBB_SEL2_REG	0x0412
+#define AB8500_REGU_VSMPS1_SEL1_REG	0x0413
+#define AB8500_REGU_VSMPS1_SEL2_REG	0x0414
+#define AB8500_REGU_VSMPS1_SEL3_REG	0x0415
+#define AB8500_REGU_VSMPS2_SEL1_REG	0x0417
+#define AB8500_REGU_VSMPS2_SEL2_REG	0x0418
+#define AB8500_REGU_VSMPS2_SEL3_REG	0x0419
+#define AB8500_REGU_VSMPS3_SEL1_REG	0x041B
+#define AB8500_REGU_VSMPS3_SEL2_REG	0x041C
+#define AB8500_REGU_VSMPS3_SEL3_REG	0x041D
+#define AB8500_REGU_VAUX1_SEL_REG	0x041F
+#define AB8500_REGU_VAUX1_SEL_MASK     0xf
+#define AB8500_REGU_VAUX1_SEL_SHIFT    0
+#define AB8500_REGU_VAUX1_SEL_1_5V     0x4
+#define AB8500_REGU_VAUX1_SEL_2_5V     0x8
+#define AB8500_REGU_VAUX2_SEL_REG	0x0420
+#define AB8500_REGU_VRF1VAUX3_SEL_REG	0x0421
+#define AB8500_REGU_CTRL2_SPARE_REG	0x0422
+
+/*
+ * Regu control2 Vmod register offsets
+ */
+#define AB8500_REGU_VMOD_REGU_REG	0x0440
+#define AB8500_REGU_VMOD_SEL1_REG	0x0441
+#define AB8500_REGU_VMOD_SEL2_REG	0x0442
+#define AB8500_REGU_CTRL_DISCH_REG	0x0443
+#define AB8500_REGU_CTRL_DISCH2_REG	0x0444
+
+/*
+ * Sim control register offsets
+ * Bank:0x4
+ */
+#define AB8500_SIM_REG1_SGR1L_REG		0x0480
+#define AB8500_SIM_REG1_SGR1U_REG		0x0481
+#define AB8500_SIM_REG2_SCR1L_REG		0x0482
+#define AB8500_SIM_REG2_SCR1U_REG		0x0483
+#define AB8500_SIM_REG3_SCTRLRL_REG		0x0484
+#define AB8500_SIM_REG3_SCTRLRU_REG		0x0485
+#define AB8500_SIM_ISOUICCINT_SRC_REG		0x0486
+#define AB8500_SIM_ISOUICCINT_LATCH_REG	0x0487
+#define AB8500_SIM_ISOUICCINT_MASK_REG		0x0488
+#define AB8500_SIM_REG4_USBUICC_REG		0x0489
+#define AB8500_SIM_SDELAYSEL_REG		0x048A
+#define AB8500_SIM_USBUICC_CTRL		0x048B	/* bit 3 only for ED */
+
+/*
+ * USB/ULPI register offsets
+ * Bank : 0x5
+ */
+#define AB8500_USB_LINE_STAT_REG	0x0580
+#define AB8500_USB_LINE_CTRL1_REG	0x0581
+#define AB8500_USB_LINE_CTRL2_REG	0x0582
+#define AB8500_USB_LINE_CTRL3_REG	0x0583
+#define AB8500_USB_LINE_CTRL4_REG	0x0584
+#define AB8500_USB_LINE_CTRL5_REG	0x0585
+#define AB8500_USB_OTG_CTRL_REG	0x0587
+#define AB8500_USB_OTG_STAT_REG	0x0588
+#define AB8500_USB_OTG_STAT_REG	0x0588
+#define AB8500_USB_CTRL_SPARE_REG	0x0589
+#define AB8500_USB_PHY_CTRL_REG	0x058A	/*only in Cut1.0*/
+
+/*
+ * TVOUT / CTRL register offsets
+ * Bank : 0x06
+ */
+#define AB8500_DENC_CONF0_REG  0x0600
+#define AB8500_DENC_CONF1_REG  0x0601
+#define AB8500_DENC_CONF2_REG  0x0602
+#define AB8500_DENC_CONF3_REG  0x0603
+#define AB8500_DENC_CONF4_REG  0x0604
+#define AB8500_DENC_CONF5_REG  0x0605
+#define AB8500_DENC_CONF6_REG  0x0606
+#define AB8500_DENC_CONF6_SOFT_RST_MASK                0x80
+#define AB8500_DENC_CONF6_SOFT_RST_SHIFT       7
+#define AB8500_DENC_CONF6_SOFT_RST_OFF         0x0
+#define AB8500_DENC_CONF6_SOFT_RST_ON          0x1
+#define AB8500_DENC_CONF7_REG  0x0607
+#define AB8500_DENC_CONF8_REG  0x0608
+#define AB8500_TVOUT_CTRL_REG	0x0680
+#define AB8500_TVOUT_CTRL2_REG 0x0681
+/*
+ * DBI register offsets
+ * Bank : 0x07
+ */
+#define AB8500_DBI_REG1_REG	0x0700
+#define AB8500_DBI_REG2_REG	0x0701
+/*
+ * ECI regsiter offsets
+ * Bank : 0x08
+ */
+#define AB8500_ECI_CTRL_REG		0x0800
+#define AB8500_ECI_HOOKLEVEL_REG	0x0801
+#define AB8500_ECI_DATAOUT_REG		0x0802
+#define AB8500_ECI_DATAIN_REG		0x0803
+/*
+ * AV Connector register offsets
+ * Bank : 0x08
+ */
+#define AB8500_AV_CONN_REG	0x0840
+/*
+ * Accessory detection register offsets
+ * Bank : 0x08
+ */
+#define AB8500_ACC_DET_DB1_REG	0x0880
+#define AB8500_ACC_DET_DB2_REG	0x0881
+/*
+ * GPADC register offsets
+ * Bank : 0x0A
+ */
+#define AB8500_GPADC_CTRL1_REG		0x0A00
+#define AB8500_GPADC_CTRL2_REG		0x0A01
+#define AB8500_GPADC_CTRL3_REG		0x0A02
+#define AB8500_GPADC_AUTO_TIMER_REG	0x0A03
+#define AB8500_GPADC_STAT_REG		0x0A04
+#define AB8500_GPADC_MANDATAL_REG	0x0A05
+#define AB8500_GPADC_MANDATAH_REG	0x0A06
+#define AB8500_GPADC_AUTODATAL_REG	0x0A07
+#define AB8500_GPADC_AUTODATAH_REG	0x0A08
+#define AB8500_GPADC_MUX_CTRL_REG	0x0A09
+/*
+ * Charger / status register offfsets
+ * Bank : 0x0B
+ */
+#define AB8500_CH_STATUS1_REG		0x0B00
+#define AB8500_CH_STATUS2_REG		0x0B01
+#define AB8500_CH_USBCH_STAT1_REG	0x0B02
+#define AB8500_CH_USBCH_STAT2_REG	0x0B03
+#define AB8500_CH_FSM_STAT_REG		0x0B04
+#define AB8500_CH_STAT_REG		0x0B05
+/*
+ * Charger / control register offfsets
+ * Bank : 0x0B
+ */
+#define AB8500_CH_VOLT_LVL_REG		0x0B40
+#define AB8500_CH_VOLT_LVL_MAX_REG	0x0B41	/*Only in Cut1.0*/
+#define AB8500_CH_OPT_CRNTLVL_REG	0x0B42	/*Only in Cut1.0*/
+#define AB8500_CH_OPT_CRNTLVL_MAX_REG	0x0B43	/*Only in Cut1.0*/
+#define AB8500_CH_WD_TIMER_REG		0x0B44	/*Only in Cut1.0*/
+#define AB8500_CH_WD_CTRL_REG		0x0B45	/*Only in Cut1.0*/
+#define AB8500_CHARG_WD_CTRL            0x0B51
+#define AB8500_LED_INDICATOR_PWM_CTRL   0x0B53
+#define AB8500_LED_INDICATOR_PWM_DUTY   0x0B54
+#define AB8500_BATT_OVV                 0x0B55
+/*
+ * Charger / main control register offfsets
+ * Bank : 0x0B
+ */
+#define AB8500_MCH_CTRL1		0x0B80
+#define AB8500_MCH_CTRL2		0x0B81
+#define AB8500_MCH_IPT_CURLVL_REG	0x0B82
+#define AB8500_CH_WD_REG		0x0B83
+/*
+ * Charger / USB control register offsets
+ * Bank : 0x0B
+ */
+#define AB8500_USBCH_CTRL1_REG		0x0BC0
+#define AB8500_USBCH_CTRL2_REG		0x0BC1
+#define AB8500_USBCH_IPT_CRNTLVL_REG	0x0BC2
+/*
+ * Gas Gauge register offsets
+ * Bank : 0x0C
+ */
+#define AB8500_GASG_CC_CTRL_REG	0x0C00
+#define AB8500_GASG_CC_ACCU1_REG	0x0C01
+#define AB8500_GASG_CC_ACCU2_REG	0x0C02
+#define AB8500_GASG_CC_ACCU3_REG	0x0C03
+#define AB8500_GASG_CC_ACCU4_REG	0x0C04
+#define AB8500_GASG_CC_SMPL_CNTRL_REG	0x0C05
+#define AB8500_GASG_CC_SMPL_CNTRH_REG	0x0C06
+#define AB8500_GASG_CC_SMPL_CNVL_REG	0x0C07
+#define AB8500_GASG_CC_SMPL_CNVH_REG	0x0C08
+#define AB8500_GASG_CC_CNTR_AVGOFF_REG	0x0C09
+#define AB8500_GASG_CC_OFFSET_REG	0x0C0A
+#define AB8500_GASG_CC_NCOV_ACCU        0x0C10
+#define AB8500_GASG_CC_NCOV_ACCU_CTRL   0x0C11
+#define AB8500_GASG_CC_NCOV_ACCU_LOW    0x0C12
+#define AB8500_GASG_CC_NCOV_ACCU_MED    0x0C13
+#define AB8500_GASG_CC_NCOV_ACCU_HIGH   0x0C14
+
+
+
+/*
+ * Audio
+ * Bank : 0x0D
+ * Should be part of Audio codec driver
+ */
+#define AB8500_AUDIO_POWER_UP		0x0D00
+#define AB8500_AUDIO_ANA_CONF4		0x0D08
+#define AB8500_AUDIO_DA_PATH_CONF	0x0D09
+#define AB8500_AUDIO_PWM_GEN_CONF1	0x0D0F
+#define AB8500_AUDIO_PWM_GEN_CONF2	0x0D10
+#define AB8500_AUDIO_PWM_GEN_CONF3	0x0D11
+#define AB8500_AUDIO_PWM_GEN_CONF4	0x0D12
+#define AB8500_AUDIO_PWM_GEN_CONF5	0x0D13
+
+/*
+ * Interrupt register offsets
+ * Bank : 0x0E
+ */
+#define AB8500_IT_SOURCE1_REG	0x0E00
+#define AB8500_IT_SOURCE2_REG	0x0E01
+#define AB8500_IT_SOURCE3_REG	0x0E02
+#define AB8500_IT_SOURCE4_REG	0x0E03
+#define AB8500_IT_SOURCE5_REG	0x0E04
+#define AB8500_IT_SOURCE6_REG	0x0E05
+
+/* available only in 1.0 */
+#define AB8500_IT_SOURCE7_REG	0x0E06
+#define AB8500_IT_SOURCE8_REG	0x0E07
+#define AB8500_IT_SOURCE19_REG	0x0E12
+
+#define AB8500_IT_SOURCE20_REG	0x0E13
+#define AB8500_IT_SOURCE21_REG	0x0E14
+#define AB8500_IT_SOURCE22_REG	0x0E15
+#define AB8500_IT_SOURCE23_REG	0x0E16
+#define AB8500_IT_SOURCE24_REG	0x0E17
+
+/*
+ * latch registers
+ */
+#define AB8500_IT_LATCH1_REG	0x0E20
+#define AB8500_IT_LATCH2_REG	0x0E21
+#define AB8500_IT_LATCH3_REG	0x0E22
+#define AB8500_IT_LATCH4_REG	0x0E23
+#define AB8500_IT_LATCH5_REG	0x0E24
+#define AB8500_IT_LATCH6_REG	0x0E25
+
+/* available only in 1.0 */
+#define AB8500_IT_LATCH7_REG	0x0E26
+#define AB8500_IT_LATCH8_REG	0x0E27
+#define AB8500_IT_LATCH9_REG	0x0E28
+#define AB8500_IT_LATCH10_REG	0x0E29
+#define AB8500_IT_LATCH19_REG	0x0E32
+
+#define AB8500_IT_LATCH20_REG	0x0E33
+#define AB8500_IT_LATCH21_REG	0x0E34
+#define AB8500_IT_LATCH22_REG	0x0E35
+#define AB8500_IT_LATCH23_REG	0x0E36
+#define AB8500_IT_LATCH24_REG	0x0E37
+
+/*
+ * mask registers
+ */
+
+#define AB8500_IT_MASK1_REG	0x0E40
+#define AB8500_IT_MASK2_REG	0x0E41
+#define AB8500_IT_MASK3_REG	0x0E42
+#define AB8500_IT_MASK4_REG	0x0E43
+#define AB8500_IT_MASK5_REG	0x0E44
+#define AB8500_IT_MASK6_REG	0x0E45
+
+
+/* available only in 1.0 */
+#define AB8500_IT_MASK7_REG	0x0E46
+#define AB8500_IT_MASK8_REG	0x0E47
+#define AB8500_IT_MASK9_REG	0x0E48
+#define AB8500_IT_MASK10_REG	0x0E49
+#define AB8500_IT_MASK11_REG	0x0E4A
+#define AB8500_IT_MASK12_REG	0x0E4B
+#define AB8500_IT_MASK13_REG	0x0E4C
+#define AB8500_IT_MASK14_REG	0x0E4D
+#define AB8500_IT_MASK15_REG	0x0E4E
+#define AB8500_IT_MASK16_REG	0x0E4F
+#define AB8500_IT_MASK17_REG	0x0E50
+#define AB8500_IT_MASK18_REG	0x0E51
+#define AB8500_IT_MASK19_REG	0x0E52
+
+#define AB8500_IT_MASK20_REG	0x0E53
+#define AB8500_IT_MASK21_REG	0x0E54
+#define AB8500_IT_MASK22_REG	0x0E55
+#define AB8500_IT_MASK23_REG	0x0E56
+#define AB8500_IT_MASK24_REG	0x0E57
+
+/*
+ * RTC bank register offsets
+ * Bank : 0xF
+ */
+#define AB8500_RTC_SWITCHOFF_STAT_REG	0x0F00
+#define AB8500_RTC_CC_CONF_REG		0x0F01
+#define AB8500_RTC_READ_REQ_REG	0x0F02
+#define AB8500_RTC_WATCH_TSECMID_REG	0x0F03
+#define AB8500_RTC_WATCH_TSECHI_REG	0x0F04
+#define AB8500_RTC_WATCH_TMIN_LOW_REG	0x0F05
+#define AB8500_RTC_WATCH_TMIN_MID_REG	0x0F06
+#define AB8500_RTC_WATCH_TMIN_HI_REG	0x0F07
+#define AB8500_RTC_ALRM_MIN_LOW_REG	0x0F08
+#define AB8500_RTC_ALRM_MIN_MID_REG	0x0F09
+#define AB8500_RTC_ALRM_MIN_HI_REG	0x0F0A
+#define AB8500_RTC_STAT_REG		0x0F0B
+#define AB8500_RTC_BKUP_CHG_REG	0x0F0C
+#define AB8500_RTC_FORCE_BKUP_REG	0x0F0D
+#define AB8500_RTC_CALIB_REG		0x0F0E
+#define AB8500_RTC_SWITCH_STAT_REG	0x0F0F
+
+/*
+ * Misc block GPIO register offsets - Not for ED
+ * Bank : 0x10
+ */
+/* available only in 1.0 */
+#define AB8500_GPIO_SEL1_REG	0x01000
+#define AB8500_GPIO_SEL2_REG	0x01001
+#define AB8500_GPIO_SEL3_REG	0x01002
+#define AB8500_GPIO_SEL4_REG	0x01003
+#define AB8500_GPIO_SEL5_REG	0x01004
+#define AB8500_GPIO_SEL6_REG	0x01005
+#define AB8500_GPIO_DIR1_REG	0x01010
+#define AB8500_GPIO_DIR2_REG	0x01011
+#define AB8500_GPIO_DIR3_REG	0x01012
+#define AB8500_GPIO_DIR4_REG	0x01013
+#define AB8500_GPIO_DIR5_REG	0x01014
+#define AB8500_GPIO_DIR6_REG	0x01015
+
+#define AB8500_GPIO_OUT1_REG	0x01020
+#define AB8500_GPIO_OUT2_REG	0x01021
+#define AB8500_GPIO_OUT3_REG	0x01022
+#define AB8500_GPIO_OUT4_REG	0x01023
+#define AB8500_GPIO_OUT5_REG	0x01024
+#define AB8500_GPIO_OUT6_REG	0x01025
+
+#define AB8500_GPIO_PUD1_REG	0x01030
+#define AB8500_GPIO_PUD2_REG	0x01031
+#define AB8500_GPIO_PUD3_REG	0x01032
+#define AB8500_GPIO_PUD4_REG	0x01033
+#define AB8500_GPIO_PUD5_REG	0x01034
+#define AB8500_GPIO_PUD6_REG	0x01035
+
+#define AB8500_GPIO_IN1_REG	0x01040
+#define AB8500_GPIO_IN2_REG	0x01041
+#define AB8500_GPIO_IN3_REG	0x01042
+#define AB8500_GPIO_IN4_REG	0x01043
+#define AB8500_GPIO_IN5_REG	0x01044
+#define AB8500_GPIO_IN6_REG	0x01045
+#define AB8500_GPIO_ALT_FUNC	0x01050
+
+/*
+ * PWM Out generators
+ * Bank: 0x10
+ */
+#define AB8500_PWM_OUT_CTRL1_REG	0x1060
+#define AB8500_PWM_OUT_CTRL2_REG	0x1061
+#define AB8500_PWM_OUT_CTRL3_REG	0x1062
+#define AB8500_PWM_OUT_CTRL4_REG	0x1063
+#define AB8500_PWM_OUT_CTRL5_REG	0x1064
+#define AB8500_PWM_OUT_CTRL6_REG	0x1065
+#define AB8500_PWM_OUT_CTRL7_REG	0x1066
+
+#define AB8500_I2C_PAD_CTRL_REG	0x1067
+#define AB8500_REV_REG			0x1080
+
+/*
+ * Misc, Debug Test Configuration register
+ * Bank : 0x11
+ */
+#define AB8500_DEBUG_TESTMODE_REG	0x01100
+
+/* only in 1.0 */
+#define AB8500_I2C_TRIG1_ADR_REG	0x1101
+#define AB8500_I2C_TRIG1_ID_REG	0x1102
+#define AB8500_I2C_TRIG2_ADR_REG	0x1103
+#define AB8500_I2C_TRIG3_ID_REG	0x1104
+#define AB8500_I2C_NOACCESS_SUP_REG	0x1105
+
+/* Offsets in TurnOnstatus register
+ */
+
+#define AB8500_MAX_INT		192
+#define AB8500_MAX_FUTURE_USE	105
+
+#define AB8500_MAX_INT_SOURCE	11
+#define AB8500_MAX_INT_LATCH	13
+#define AB8500_MAX_INT_MASK	21
+
+#define ab8500_read	prcmu_i2c_read
+#define ab8500_write	prcmu_i2c_write
+
+extern int prcmu_i2c_read(u8 reg, u16 slave);
+extern int prcmu_i2c_write(u8 reg, u16 slave, u8 reg_data);
+
+#endif /* AB8500_H_ */
diff --git a/arch/arm/include/asm/arch-u8500/bits.h b/arch/arm/include/asm/arch-u8500/bits.h
new file mode 100644
index 0000000..17e2f09
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/bits.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef __bits_h
+#define __bits_h 1
+
+#define BIT0  (1<<0)
+#define BIT1  (1<<1)
+#define BIT2  (1<<2)
+#define BIT3  (1<<3)
+#define BIT4  (1<<4)
+#define BIT5  (1<<5)
+#define BIT6  (1<<6)
+#define BIT7  (1<<7)
+#define BIT8  (1<<8)
+#define BIT9  (1<<9)
+#define BIT10 (1<<10)
+#define BIT11 (1<<11)
+#define BIT12 (1<<12)
+#define BIT13 (1<<13)
+#define BIT14 (1<<14)
+#define BIT15 (1<<15)
+#define BIT16 (1<<16)
+#define BIT17 (1<<17)
+#define BIT18 (1<<18)
+#define BIT19 (1<<19)
+#define BIT20 (1<<20)
+#define BIT21 (1<<21)
+#define BIT22 (1<<22)
+#define BIT23 (1<<23)
+#define BIT24 (1<<24)
+#define BIT25 (1<<25)
+#define BIT26 (1<<26)
+#define BIT27 (1<<27)
+#define BIT28 (1<<28)
+#define BIT29 (1<<29)
+#define BIT30 (1<<30)
+#define BIT31 (1<<31)
+
+#endif
diff --git a/arch/arm/include/asm/arch-u8500/clock.h b/arch/arm/include/asm/arch-u8500/clock.h
new file mode 100644
index 0000000..b00ab0d
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/clock.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_ARCH_CLOCK
+#define __ASM_ARCH_CLOCK
+
+struct prcmu {
+	unsigned int armclkfix_mgt;
+	unsigned int armclk_mgt;
+	unsigned int svammdspclk_mgt;
+	unsigned int siammdspclk_mgt;
+	unsigned int reserved;
+	unsigned int sgaclk_mgt;
+	unsigned int uartclk_mgt;
+	unsigned int msp02clk_mgt;
+	unsigned int i2cclk_mgt;
+	unsigned int sdmmcclk_mgt;
+	unsigned int slimclk_mgt;
+	unsigned int per1clk_mgt;
+	unsigned int per2clk_mgt;
+	unsigned int per3clk_mgt;
+	unsigned int per5clk_mgt;
+	unsigned int per6clk_mgt;
+	unsigned int per7clk_mgt;
+	unsigned int lcdclk_mgt;
+	unsigned int reserved1;
+	unsigned int bmlclk_mgt;
+	unsigned int hsitxclk_mgt;
+	unsigned int hsirxclk_mgt;
+	unsigned int hdmiclk_mgt;
+	unsigned int apeatclk_mgt;
+	unsigned int apetraceclk_mgt;
+	unsigned int mcdeclk_mgt;
+	unsigned int ipi2cclk_mgt;
+	unsigned int dsialtclk_mgt;
+	unsigned int spare2clk_mgt;
+	unsigned int dmaclk_mgt;
+	unsigned int b2r2clk_mgt;
+	unsigned int tvclk_mgt;
+	unsigned int unused[82];
+	unsigned int tcr;
+	unsigned int unused1[23];
+	unsigned int ape_softrst;
+};
+
+extern void u8500_clock_enable(int periph, int kern, int cluster);
+
+static inline void u8500_prcmu_enable(unsigned int *reg)
+{
+	writel(readl(reg) | (1 << 8), reg);
+}
+
+#endif /* __ASM_ARCH_CLOCK */
diff --git a/arch/arm/include/asm/arch-u8500/common.h b/arch/arm/include/asm/arch-u8500/common.h
new file mode 100644
index 0000000..ab8a4db
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/common.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _COMMON_H_
+#define _COMMON_H_
+#include <common.h>
+
+#define PASS (1)
+#define FAIL (0)
+
+#define IO(addr)  (*((u32 *) (addr)))
+#define HIO(addr) (*((u16 *) (addr)))
+#define BIO(addr) (*((u8 *)  (addr)))
+
+/*
+ * macro to get at IO space
+ */
+#define IO_ADDRESS(x) (x)
+
+#define REG_WRITE_BITS(reg, val, mask, sb) \
+	(writel(((readl(reg) & ~(mask)) | (((val)<<(sb)) & (mask))), reg))
+
+#define nmdk_error(format, arg...) printf(": " format "\n" , ## arg)
+
+/*-----------------------------------------------------------------------------
+ * Bit mask definition
+ *---------------------------------------------------------------------------*/
+#define MASK_NULL8    0x00
+#define MASK_NULL16   0x0000
+#define MASK_NULL32   0x00000000
+#define MASK_ALL8     0xFF
+#define MASK_ALL16    0xFFFF
+#define MASK_ALL32    0xFFFFFFFF
+
+#define MASK_BIT0     (1UL<<0)
+#define MASK_BIT1     (1UL<<1)
+#define MASK_BIT2     (1UL<<2)
+#define MASK_BIT3     (1UL<<3)
+#define MASK_BIT4     (1UL<<4)
+#define MASK_BIT5     (1UL<<5)
+#define MASK_BIT6     (1UL<<6)
+#define MASK_BIT7     (1UL<<7)
+#define MASK_BIT8     (1UL<<8)
+#define MASK_BIT9     (1UL<<9)
+#define MASK_BIT10    (1UL<<10)
+#define MASK_BIT11    (1UL<<11)
+#define MASK_BIT12    (1UL<<12)
+#define MASK_BIT13    (1UL<<13)
+#define MASK_BIT14    (1UL<<14)
+#define MASK_BIT15    (1UL<<15)
+#define MASK_BIT16    (1UL<<16)
+#define MASK_BIT17    (1UL<<17)
+#define MASK_BIT18    (1UL<<18)
+#define MASK_BIT19    (1UL<<19)
+#define MASK_BIT20    (1UL<<20)
+#define MASK_BIT21    (1UL<<21)
+#define MASK_BIT22    (1UL<<22)
+#define MASK_BIT23    (1UL<<23)
+#define MASK_BIT24    (1UL<<24)
+#define MASK_BIT25    (1UL<<25)
+#define MASK_BIT26    (1UL<<26)
+#define MASK_BIT27    (1UL<<27)
+#define MASK_BIT28    (1UL<<28)
+#define MASK_BIT29    (1UL<<29)
+#define MASK_BIT30    (1UL<<30)
+#define MASK_BIT31    (1UL<<31)
+
+#define NOMADIK_INTERNAL_ERROR                  (-8)
+#define NOMADIK_NOT_CONFIGURED                  (-7)
+#define NOMADIK_REQUEST_PENDING                 (-6)
+#define NOMADIK_REQUEST_NOT_APPLICABLE          (-5)
+#define NOMADIK_INVALID_PARAMETER               (-4)
+#define NOMADIK_UNSUPPORTED_FEATURE             (-3)
+#define NOMADIK_UNSUPPORTED_HW                  (-2)
+#define NOMADIK_ERROR                           (-1)
+#define NOMADIK_OK                              (0)
+#define NOMADIK_INTERNAL_EVENT                  (1)
+#define NOMADIK_REMAINING_PENDING_EVENTS        (2)
+#define NOMADIK_REMAINING_FILTER_PENDING_EVENTS (3)
+#define NOMADIK_NO_MORE_PENDING_EVENT           (4)
+#define NOMADIK_NO_MORE_FILTER_PENDING_EVENT    (5)
+#define NOMADIK_NO_PENDING_EVENT_ERROR          (7)
+
+
+void gpio_init(void);
+void arm_pl180_mmci_init(void);
+
+
+#endif  /* _COMMON_H_ */
diff --git a/arch/arm/include/asm/arch-u8500/gpio.h b/arch/arm/include/asm/arch-u8500/gpio.h
new file mode 100644
index 0000000..39982a6
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/gpio.h
@@ -0,0 +1,247 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _UX500_GPIO_h
+#define _UX500_GPIO_h
+
+#include <asm/types.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+
+#include "common.h"
+#include <asm/arch/u8500.h>
+
+#define GPIO_TOTAL_PINS                 268
+
+#define GPIO_PINS_PER_BLOCK	32
+#define GPIO_BLOCKS_COUNT       (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1)
+#define GPIO_BLOCK(pin)		(((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1)
+
+
+struct gpio_register {
+	u32 gpio_dat;	/* data register *//*0x000 */
+	u32 gpio_dats;	/* data Set register *//*0x004 */
+	u32 gpio_datc;	/* data Clear register *//*0x008 */
+	u32 gpio_pdis;	/* Pull disable register *//*0x00C */
+	u32 gpio_dir;	/* data direction register *//*0x010 */
+	u32 gpio_dirs;	/* data dir Set register *//*0x014 */
+	u32 gpio_dirc;	/* data dir Clear register *//*0x018 */
+	u32 gpio_slpm;	/* Sleep mode register *//*0x01C */
+	u32 gpio_afsa;	/* AltFun A Select reg *//*0x020 */
+	u32 gpio_afsb;	/* AltFun B Select reg *//*0x024 */
+	u32 gpio_lowemi;/* low EMI Select reg *//*0x028 */
+	u32 reserved_1[(0x040 - 0x02C) >> 2];	/*0x028-0x3C Reserved*/
+	u32 gpio_rimsc;	/* rising edge intr set/clear *//*0x040 */
+	u32 gpio_fimsc;	/* falling edge intr set/clear register *//*0x044 */
+	u32 gpio_mis;	/* masked interrupt status register *//*0x048 */
+	u32 gpio_ic;	/* Interrupt Clear register *//*0x04C */
+	u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register *//*0x050 */
+	u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register *//*0x054 */
+	u32 gpio_wks;	/* Wakeup Status register *//*0x058 */
+};
+
+/* Error values returned by functions */
+enum gpio_error {
+	GPIO_OK = 0,
+	GPIO_UNSUPPORTED_HW = -2,	/* NOMADIK_UNSUPPORTED_HW */
+	GPIO_UNSUPPORTED_FEATURE = -3,	/* NOMADIK_UNSUPPORTED_FEATURE */
+	GPIO_INVALID_PARAMETER = -4,	/* NOMADIK_INVALID_PARAMETER */
+	GPIO_REQUEST_NOT_APPLICABLE = -5, /* NOMADIK_REQUEST_NOT_APPLICABLE */
+	GPIO_REQUEST_PENDING = -6,	/* NOMADIK_REQUEST_PENDING */
+	GPIO_NOT_CONFIGURED = -7,	/* NOMADIK_NOT_CONFIGURED */
+	GPIO_INTERNAL_ERROR = -8,	/* NOMADIK_INTERNAL_ERROR */
+	GPIO_INTERNAL_EVENT = 1,	/* NOMADIK_INTERNAL_EVENT */
+	GPIO_REMAINING_EVENT = 2,	/* NOMADIK_REMAINING_PENDING_EVENTS */
+	GPIO_NO_MORE_PENDING_EVENT = 3,	/* NOMADIK_NO_MORE_PENDING_EVENT */
+	GPIO_INVALID_CLIENT = -25,
+	GPIO_INVALID_PIN = -26,
+	GPIO_PIN_BUSY = -27,
+	GPIO_PIN_NOT_ALLOCATED = -28,
+	GPIO_WRONG_CLIENT = -29,
+	GPIO_UNSUPPORTED_ALTFUNC = -30,
+};
+
+/*GPIO DEVICE ID */
+enum gpio_device_id {
+	GPIO_DEVICE_ID_0,
+	GPIO_DEVICE_ID_1,
+	GPIO_DEVICE_ID_2,
+	GPIO_DEVICE_ID_3,
+	GPIO_DEVICE_ID_INVALID
+};
+
+/*
+ * Alternate Function:
+ *  refered in altfun_table to pointout particular altfun to be enabled
+ *  when using GPIO_ALT_FUNCTION A/B/C enable/disable operation
+ */
+enum gpio_alt_function {
+	GPIO_ALT_UART_0_MODEM,
+	GPIO_ALT_UART_0_NO_MODEM,
+	GPIO_ALT_UART_1,
+	GPIO_ALT_UART_2,
+	GPIO_ALT_I2C_0,
+	GPIO_ALT_I2C_1,
+	GPIO_ALT_I2C_2,
+	GPIO_ALT_I2C_3,
+	GPIO_ALT_MSP_0,
+	GPIO_ALT_MSP_1,
+	GPIO_ALT_MSP_2,
+	GPIO_ALT_MSP_3,
+	GPIO_ALT_MSP_4,
+	GPIO_ALT_MSP_5,
+	GPIO_ALT_SSP_0,
+	GPIO_ALT_SSP_1,
+	GPIO_ALT_MM_CARD0,
+	GPIO_ALT_SD_CARD0,
+	GPIO_ALT_DMA_0,
+	GPIO_ALT_DMA_1,
+	GPIO_ALT_HSI0,
+	GPIO_ALT_CCIR656_INPUT,
+	GPIO_ALT_CCIR656_OUTPUT,
+	GPIO_ALT_LCD_PANEL,
+	GPIO_ALT_MDIF,
+	GPIO_ALT_SDRAM,
+	GPIO_ALT_HAMAC_AUDIO_DBG,
+	GPIO_ALT_HAMAC_VIDEO_DBG,
+	GPIO_ALT_CLOCK_RESET,
+	GPIO_ALT_TSP,
+	GPIO_ALT_IRDA,
+	GPIO_ALT_USB_MINIMUM,
+	GPIO_ALT_USB_I2C,
+	GPIO_ALT_OWM,
+	GPIO_ALT_PWL,
+	GPIO_ALT_FSMC,
+	GPIO_ALT_COMP_FLASH,
+	GPIO_ALT_SRAM_NOR_FLASH,
+	GPIO_ALT_FSMC_ADDLINE_0_TO_15,
+	GPIO_ALT_SCROLL_KEY,
+	GPIO_ALT_MSHC,
+	GPIO_ALT_HPI,
+	GPIO_ALT_USB_OTG,
+	GPIO_ALT_SDIO,
+	GPIO_ALT_HSMMC,
+	GPIO_ALT_FSMC_ADD_DATA_0_TO_25,
+	GPIO_ALT_HSI1,
+	GPIO_ALT_NOR,
+	GPIO_ALT_NAND,
+	GPIO_ALT_KEYPAD,
+	GPIO_ALT_VPIP,
+	GPIO_ALT_CAM,
+	GPIO_ALT_CCP1,
+	GPIO_ALT_EMMC,
+	GPIO_ALT_POP_EMMC,
+	GPIO_ALT_FUNMAX		/* Add new alt func before this */
+};
+
+/* Defines pin assignment(Software mode or Alternate mode) */
+enum gpio_mode {
+	GPIO_MODE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_MODE_SOFTWARE,	/* Pin connected to GPIO (SW controlled) */
+	GPIO_ALTF_A,		/* Pin connected to altfunc 1 (HW periph 1) */
+	GPIO_ALTF_B,		/* Pin connected to altfunc 2 (HW periph 2) */
+	GPIO_ALTF_C,		/* Pin connected to altfunc 3 (HW periph 3) */
+	GPIO_ALTF_FIND,		/* Pin connected to altfunc 3 (HW periph 3) */
+	GPIO_ALTF_DISABLE	/* Pin connected to altfunc 3 (HW periph 3) */
+};
+
+/* Defines GPIO pin direction */
+enum gpio_direction {
+	GPIO_DIR_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_DIR_INPUT,		/* GPIO set as input */
+	GPIO_DIR_OUTPUT		/* GPIO set as output */
+};
+
+/* Interrupt trigger mode */
+enum gpio_trig {
+	GPIO_TRIG_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_TRIG_DISABLE,	/* Trigger no IT */
+	GPIO_TRIG_RISING_EDGE,	/* Trigger an IT on rising edge */
+	GPIO_TRIG_FALLING_EDGE,	/* Trigger an IT on falling edge */
+	GPIO_TRIG_BOTH_EDGES,	/* Trigger an IT on rising and falling edge */
+	GPIO_TRIG_HIGH_LEVEL,	/* Trigger an IT on high level */
+	GPIO_TRIG_LOW_LEVEL	/* Trigger an IT on low level */
+};
+
+/* Configuration parameters for one GPIO pin.*/
+struct gpio_config {
+	enum gpio_mode mode;
+	enum gpio_direction direction;
+	enum gpio_trig trig;
+	char *dev_name;		/* Who owns the gpio pin */
+};
+
+/* GPIO pin data*/
+enum gpio_data {
+	GPIO_DATA_LOW,
+	GPIO_DATA_HIGH
+};
+
+/* GPIO behaviour in sleep mode */
+enum gpio_sleep_mode {
+	GPIO_SLEEP_MODE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT,	/* GPIO is an input with pull
+						   up/down enabled when in sleep
+						   mode. */
+	GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO	/* GPIO pin is controlled by
+						   GPIO IP. So mode, direction
+						   and data values for GPIO pin
+						   in sleep mode are determined
+						   by configuration set to GPIO
+						   pin before entering to sleep
+						   mode. */
+};
+
+/* GPIO ability to wake the system up from sleep mode.*/
+enum gpio_wake {
+	GPIO_WAKE_LEAVE_UNCHANGED,	/* Parameter will be ignored */
+	GPIO_WAKE_DISABLE,	/* No wake of system from sleep mode. */
+	GPIO_WAKE_LOW_LEVEL,	/* Wake the system up on a LOW level. */
+	GPIO_WAKE_HIGH_LEVEL,	/* Wake the system up on a HIGH level. */
+	GPIO_WAKE_RISING_EDGE,	/* Wake the system up on a RISING edge. */
+	GPIO_WAKE_FALLING_EDGE,	/* Wake the system up on a FALLING edge. */
+	GPIO_WAKE_BOTH_EDGES	/* Wake the system up on both RISE and FALL. */
+};
+
+/* Configuration parameters for one GPIO pin in sleep mode.*/
+struct gpio_sleep_config {
+	enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */
+	enum gpio_wake wake;		/* GPIO ability to wake up system. */
+};
+
+extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config);
+extern int gpio_resetpinconfig(int pin_id, char *dev_name);
+extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name);
+extern int gpio_readpin(int pin_id, enum gpio_data *value);
+extern int gpio_altfuncenable(enum gpio_alt_function altfunc,
+				      char *dev_name);
+extern int gpio_altfuncdisable(enum gpio_alt_function altfunc,
+				       char *dev_name);
+
+struct gpio_altfun_data {
+	u16 altfun;
+	u16 start;
+	u16 end;
+	u16 cont;
+	u8 type;
+};
+#endif
diff --git a/arch/arm/include/asm/arch-u8500/hardware.h b/arch/arm/include/asm/arch-u8500/hardware.h
new file mode 100644
index 0000000..6bb95ec
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/hardware.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+/* Peripheral clusters */
+
+#define U8500_PER3_BASE		0x80000000
+#define U8500_PER2_BASE		0x80110000
+#define U8500_PER1_BASE		0x80120000
+#define U8500_PER4_BASE		0x80150000
+
+#define U8500_PER6_BASE		0xa03c0000
+#define U8500_PER7_BASE		0xa03d0000
+#define U8500_PER5_BASE		0xa03e0000
+
+/* GPIO */
+
+#define U8500_GPIO0_BASE	(U8500_PER1_BASE + 0xE000)
+#define U8500_GPIO1_BASE	(U8500_PER1_BASE + 0xE000 + 0x80)
+
+#define U8500_GPIO2_BASE	(U8500_PER3_BASE + 0xE000)
+#define U8500_GPIO3_BASE	(U8500_PER3_BASE + 0xE000 + 0x80)
+#define U8500_GPIO4_BASE	(U8500_PER3_BASE + 0xE000 + 0x100)
+#define U8500_GPIO5_BASE	(U8500_PER3_BASE + 0xE000 + 0x180)
+
+#define U8500_GPIO6_BASE	(U8500_PER2_BASE + 0xE000)
+#define U8500_GPIO7_BASE	(U8500_PER2_BASE + 0xE000 + 0x80)
+
+#define U8500_GPIO8_BASE	(U8500_PER5_BASE + 0x1E000)
+
+/* Per7 */
+#define U8500_CLKRST7_BASE	(U8500_PER7_BASE + 0xf000)
+
+/* Per6 */
+#define U8500_MTU0_BASE_V1	(U8500_PER6_BASE + 0x6000)
+#define U8500_MTU1_BASE_V1	(U8500_PER6_BASE + 0x7000)
+#define U8500_CLKRST6_BASE	(U8500_PER6_BASE + 0xf000)
+
+/* Per5 */
+#define U8500_CLKRST5_BASE	(U8500_PER5_BASE + 0x1f000)
+
+/* Per4 */
+#define U8500_PRCMU_BASE	(U8500_PER4_BASE + 0x07000)
+#define U8500_PRCMU_TCDM_BASE   (U8500_PER4_BASE + 0x0f000)
+
+/* Per3 */
+#define U8500_UART2_BASE	(U8500_PER3_BASE + 0x7000)
+#define U8500_CLKRST3_BASE	(U8500_PER3_BASE + 0xf000)
+
+/* Per2 */
+#define U8500_CLKRST2_BASE	(U8500_PER2_BASE + 0xf000)
+
+/* Per1 */
+#define U8500_UART0_BASE	(U8500_PER1_BASE + 0x0000)
+#define U8500_UART1_BASE	(U8500_PER1_BASE + 0x1000)
+#define U8500_CLKRST1_BASE	(U8500_PER1_BASE + 0xf000)
+
+/* Last page of Boot ROM */
+#define U8500_BOOTROM_BASE      0x9001f000
+#define U8500_BOOTROM_ASIC_ID_OFFSET    0x0ff4
+
+#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/include/asm/arch-u8500/u8500.h b/arch/arm/include/asm/arch-u8500/u8500.h
new file mode 100644
index 0000000..0d6dbb7
--- /dev/null
+++ b/arch/arm/include/asm/arch-u8500/u8500.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2009
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __U8500_H
+#define __U8500_H
+
+/*
+ * base register values for U8500
+ */
+#define CFG_PRCMU_BASE		0x80157000	/* Power, reset and clock
+						   Management Unit */
+#define CFG_SDRAMC_BASE		0x903CF000	/* SDRAMC cnf registers */
+#define CFG_FSMC_BASE		0x80000000	/* FSMC Controller */
+
+/*
+ * U8500 GPIO register base for 9 banks
+ */
+#define U8500_GPIO_0_BASE			0x8012E000
+#define U8500_GPIO_1_BASE			0x8012E080
+#define U8500_GPIO_2_BASE			0x8000E000
+#define U8500_GPIO_3_BASE			0x8000E080
+#define U8500_GPIO_4_BASE			0x8000E100
+#define U8500_GPIO_5_BASE			0x8000E180
+#define U8500_GPIO_6_BASE			0x8011E000
+#define U8500_GPIO_7_BASE			0x8011E080
+#define U8500_GPIO_8_BASE			0xA03FE000
+
+#endif	/* __U8500_H */
