From patchwork Thu Jul 5 11:59:46 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rajeshwari Shinde X-Patchwork-Id: 9835 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id D5B4E23E23 for ; Thu, 5 Jul 2012 11:55:25 +0000 (UTC) Received: from mail-gh0-f180.google.com (mail-gh0-f180.google.com [209.85.160.180]) by fiordland.canonical.com (Postfix) with ESMTP id 8E74EA18278 for ; Thu, 5 Jul 2012 11:55:25 +0000 (UTC) Received: by ghbz12 with SMTP id z12so7880500ghb.11 for ; Thu, 05 Jul 2012 04:55:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=x-forwarded-to:x-forwarded-for:delivered-to:received-spf:x-auditid :from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-brightmail-tracker:x-tm-as-mml:x-gm-message-state; bh=sIRUUvh+7gYr8T6QPLvdHxycbpbyzE7siGZIY/O+Bak=; b=hHjJv0+3eAhO2HXKVpC4tVOPhk5b3Tt8GYGbXp/vu8b9O+HmHHIhq+2eAD70ZPiLHC hIDVelN/Luaw8afDKnBp/y1WuRzZcLkFs4hjlIElKAXsmwnulis1Tf+1LSVloXfUC3fp jrbLUg+FtFmOQ4AneTtQMvD45jFhN1yOiQ6V8mNtXc7Kkg1Y4ZcAYVHrwc1ekgtmNPuQ M/ds1WLojuEwgOYlskCvgdXWrti1LWQr9UIBvqNbW+dRw9Os1ULBhfsD1/FTcUStqrB6 dbudgahw906Gm0s5FjDn6vN4e23jF3nhJ0CSdkSBoPJXZcyehRyaj4l7iM+gr0eAMEht +hgA== Received: by 10.50.57.167 with SMTP id j7mr13647107igq.53.1341489324742; Thu, 05 Jul 2012 04:55:24 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.24.148 with SMTP id v20csp64367ibb; Thu, 5 Jul 2012 04:55:24 -0700 (PDT) Received: by 10.68.197.198 with SMTP id iw6mr26954414pbc.36.1341489324019; Thu, 05 Jul 2012 04:55:24 -0700 (PDT) Received: from mailout1.samsung.com (mailout1.samsung.com. [203.254.224.24]) by mx.google.com with ESMTP id ug10si37485497pbc.245.2012.07.05.04.55.23; Thu, 05 Jul 2012 04:55:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) client-ip=203.254.224.24; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.24 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm2.samsung.com (mailout1.samsung.com [203.254.224.24]) by mailout1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M6O001WMRS24L40@mailout1.samsung.com>; Thu, 05 Jul 2012 20:55:22 +0900 (KST) X-AuditID: cbfee61b-b7f566d000005c8a-74-4ff580aa6eb6 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm2.samsung.com (EPCPMTA) with SMTP id 03.C7.23690.AA085FF4; Thu, 05 Jul 2012 20:55:22 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M6O00E8SRRY5M50@mmp2.samsung.com>; Thu, 05 Jul 2012 20:55:22 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, hs@denx.de, mk7.kang@samsung.com, chander.kashyap@linaro.org, jy0922.shim@samsung.com Subject: [PATCH 1/7 V5] EXYNOS: CLK: Add i2c clock Date: Thu, 05 Jul 2012 17:29:46 +0530 Message-id: <1341489592-24243-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1341489592-24243-1-git-send-email-rajeshwari.s@samsung.com> References: <1341489592-24243-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrOJMWRmVeSWpSXmKPExsVy+t9jQd1VDV/9DY4cU7J4uP4mi8WUw19Y HJg87lzbwxbAGMVlk5Kak1mWWqRvl8CVcfryJ+aCucIVsy7LNjBe5e9i5OSQEDCR+NKzlhHC FpO4cG89WxcjF4eQwHRGiXv/u9ghnIlMEh/f/gSrYhMwkth6chqYLSIgIfGr/yojSBGzwCxG iUVbGtlAEsJARQuPrwErYhFQlVh/cTULiM0r4CFx9+BOJoh1ChLHpn5lBbE5BTwlfvY/A+rl ANrmIXFxscwERt4FjAyrGEVTC5ILipPSc430ihNzi0vz0vWS83M3MYK9/0x6B+OqBotDjAIc jEo8vAK1X/2FWBPLiitzDzFKcDArifD2ZgCFeFMSK6tSi/Lji0pzUosPMUpzsCiJ85p4A6UE 0hNLUrNTUwtSi2CyTBycUg2M2sssVPIva6w/UhxbGXL2eczyOLmW1aKeEeeFa4442Wqttpdx nrpnVfTkltvrfvy9a9TEtXTH9Ji2ll39K5+1XJqqXMzZpvXD8HOy8opHS0V/2G8qW3agxHGH UYcOy/5FbrN+PWs/9enVs4Pz05z4HqnMcXm412dxrempiyZxKr7x9tkM81auVmIpzkg01GIu Kk4EAIfabQj6AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQltR/EeoEDqQ81olws/KZWTdWgQcCOfDlr+il63O3yE6fgUHl11/mV5qnaRIK/hSSaeju4/ This adds i2c clock information for EXYNOS5. Signed-off-by: Alim Akhtar Signed-off-by: Doug Anderson Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- changes in V2: - Incorporated comments from Simon Glass which are removed extra braces around (readl(&clk->div_top1)) >> 24 and gave a tab space for return statement. Changes in V3: - None Changes in V4: - None Changes in V5: - None. arch/arm/cpu/armv7/exynos/clock.c | 33 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 1 + 2 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index fc0ed5e..83ee25e 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -602,6 +602,29 @@ void exynos4_set_mipi_clk(void) writel(cfg, &clk->div_lcd0); } +/* + * I2C + * + * exynos5: obtaining the I2C clock + */ +static unsigned long exynos5_get_i2c_clk(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned long aclk_66, aclk_66_pre, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + + ratio = (readl(&clk->div_top1)) >> 24; + ratio &= (0x7); + aclk_66_pre = sclk/(ratio+1); + ratio = readl(&clk->div_top0); + ratio &= (0x7); + aclk_66 = aclk_66_pre/(ratio+1); + return aclk_66; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -618,6 +641,16 @@ unsigned long get_arm_clk(void) return exynos4_get_arm_clk(); } +unsigned long get_i2c_clk(void) +{ + if (cpu_is_exynos5()) { + return exynos5_get_i2c_clk(); + } else { + debug("I2C clock is not set for this CPU\n"); + return 0; + } +} + unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index e99339a..5529025 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -31,6 +31,7 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); +unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div);