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[203.254.224.33]) by mx.google.com with ESMTP id kc9si5141739pbc.295.2012.08.01.02.27.16; Wed, 01 Aug 2012 02:27:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) client-ip=203.254.224.33; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.33 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (mailout3.samsung.com [203.254.224.33]) by mailout3.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0M82003GGKWD1X40@mailout3.samsung.com>; Wed, 01 Aug 2012 18:27:15 +0900 (KST) X-AuditID: cbfee61a-b7f616d000004b7e-1d-5018f6738583 Received: from epmmp2 ( [203.254.227.17]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id AD.B5.19326.376F8105; Wed, 01 Aug 2012 18:27:15 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp2.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0M820029AKX8FS00@mmp2.samsung.com>; Wed, 01 Aug 2012 18:27:15 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 1/7 V3] EXYNOS5: Add pinmux support for SPI Date: Wed, 01 Aug 2012 15:03:26 +0530 Message-id: <1343813612-1587-2-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1343813612-1587-1-git-send-email-rajeshwari.s@samsung.com> References: <1343813612-1587-1-git-send-email-rajeshwari.s@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrGJMWRmVeSWpSXmKPExsVy+t9jQd3ibxIBBrO7LS0err/JYjHl8BcW ByaPO9f2sAUwRnHZpKTmZJalFunbJXBlTHr0mLXgnmhF549GlgbGY4JdjJwcEgImEn/37WSG sMUkLtxbz9bFyMUhJDCdUWLq5HWMEM5EJolN31vYQarYBIwktp6cxghiiwhISPzqvwpkc3Aw C5RKTJmYBxIWFrCWWLvjGAuIzSKgKtE2/ysTiM0r4C7R8HsFC8QyBYljU7+ygrRyCnhIfN/J BhIWAiq59XYX6wRG3gWMDKsYRVMLkguKk9JzDfWKE3OLS/PS9ZLzczcxgn3/TGoH48oGi0OM AhyMSjy8E00kAoRYE8uKK3MPMUpwMCuJ8BbcBArxpiRWVqUW5ccXleakFh9ilOZgURLnNfb+ 6i8kkJ5YkpqdmlqQWgSTZeLglGpgZI7qFcvmfv5FIvZPWG1Vx0Hjx6cfdM958e1g6sbjAne4 wmu8M5y/pjCdENz3T6tUcs2ckMfPuu6tmWe38Ym4Y8bH83uf97E1xO/YrCjw5YLsVN9DtUrz /6c8Wrvj1hUWdqGZDyLOcejdPlO49fpqs82ViX7ie4085frunHrU9fVrq8qbxLVtZ5VYijMS DbWYi4oTAVwsyzr5AQAA X-TM-AS-MML: No X-Gm-Message-State: ALoCoQkPxKf0IzIT67ZakdUDBdgzZ1QXPAKLQ7P3hTo3qyho5ESyThj+DS8volCLrd9YHDNvVxML This patch adds pinmux support for SPI channels Signed-off-by: Rajeshwari Shinde --- Changes in V2: - None. Changes in V3: - Removed the slave flag for SPI. arch/arm/cpu/armv7/exynos/pinmux.c | 51 ++++++++++++++++++++++++++++- arch/arm/include/asm/arch-exynos/periph.h | 5 +++ 2 files changed, 55 insertions(+), 1 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 7776add..13f75e0 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -230,6 +230,49 @@ static void exynos5_i2c_config(int peripheral, int flags) } } +void exynos5_spi_config(int peripheral) +{ + int cfg = 0, pin = 0, i; + struct s5p_gpio_bank *bank = NULL; + struct exynos5_gpio_part1 *gpio1 = + (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); + struct exynos5_gpio_part2 *gpio2 = + (struct exynos5_gpio_part2 *) samsung_get_base_gpio_part2(); + + switch (peripheral) { + case PERIPH_ID_SPI0: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI1: + bank = &gpio1->a2; + cfg = GPIO_FUNC(0x2); + pin = 4; + break; + case PERIPH_ID_SPI2: + bank = &gpio1->b1; + cfg = GPIO_FUNC(0x5); + pin = 1; + break; + case PERIPH_ID_SPI3: + bank = &gpio2->f1; + cfg = GPIO_FUNC(0x2); + pin = 0; + break; + case PERIPH_ID_SPI4: + for (i = 2; i < 4; i++) + s5p_gpio_cfg_pin(&gpio2->f0, i, GPIO_FUNC(0x4)); + for (i = 4; i < 6; i++) + s5p_gpio_cfg_pin(&gpio2->e0, i, GPIO_FUNC(0x4)); + break; + } + if (peripheral != PERIPH_ID_SPI4) { + for (i = pin; i < pin + 4; i++) + s5p_gpio_cfg_pin(bank, i, cfg); + } +} + static int exynos5_pinmux_config(int peripheral, int flags) { switch (peripheral) { @@ -257,11 +300,17 @@ static int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_I2C7: exynos5_i2c_config(peripheral, flags); break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + case PERIPH_ID_SPI3: + case PERIPH_ID_SPI4: + exynos5_spi_config(peripheral); + break; default: debug("%s: invalid peripheral %d", __func__, peripheral); return -1; } - return 0; } diff --git a/arch/arm/include/asm/arch-exynos/periph.h b/arch/arm/include/asm/arch-exynos/periph.h index b861d7d..dafc3f3 100644 --- a/arch/arm/include/asm/arch-exynos/periph.h +++ b/arch/arm/include/asm/arch-exynos/periph.h @@ -43,6 +43,11 @@ enum periph_id { PERIPH_ID_SDMMC2, PERIPH_ID_SDMMC3, PERIPH_ID_SROMC, + PERIPH_ID_SPI0, + PERIPH_ID_SPI1, + PERIPH_ID_SPI2, + PERIPH_ID_SPI3, + PERIPH_ID_SPI4, PERIPH_ID_UART0, PERIPH_ID_UART1, PERIPH_ID_UART2,