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[203.254.224.34]) by mx.google.com with ESMTP id q6si766734pay.284.2012.10.25.22.50.45; Thu, 25 Oct 2012 22:50:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) client-ip=203.254.224.34; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of rajeshwari.s@samsung.com designates 203.254.224.34 as permitted sender) smtp.mail=rajeshwari.s@samsung.com Received: from epcpsbgm1.samsung.com (epcpsbgm1 [203.254.230.26]) by mailout4.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTP id <0MCH00L8HK8AV7G0@mailout4.samsung.com>; Fri, 26 Oct 2012 14:50:45 +0900 (KST) Received: from epcpsbgm1.samsung.com ( [172.20.52.124]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id ED.A9.01231.4B42A805; Fri, 26 Oct 2012 14:50:45 +0900 (KST) X-AuditID: cbfee61a-b7fa66d0000004cf-22-508a24b4db3b Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm1.samsung.com (EPCPMTA) with SMTP id 8D.A9.01231.4B42A805; Fri, 26 Oct 2012 14:50:44 +0900 (KST) Received: from rajeshwari-linux.sisodomain.com ([107.108.215.115]) by mmp1.samsung.com (Oracle Communications Messaging Server 7u4-24.01(7.0.4.24.0) 64bit (built Nov 17 2011)) with ESMTPA id <0MCH0021JJY1HB30@mmp1.samsung.com>; Fri, 26 Oct 2012 14:50:44 +0900 (KST) From: Rajeshwari Shinde To: u-boot@lists.denx.de Cc: patches@linaro.org, alim.akhtar@samsung.com, sjg@chromium.org, mk7.kang@samsung.com, chander.kashyap@linaro.org Subject: [PATCH 8/9 V4] EXYNOS: Add clock for I2S Date: Fri, 26 Oct 2012 11:19:29 +0530 Message-id: <1351230570-21597-9-git-send-email-rajeshwari.s@samsung.com> X-Mailer: git-send-email 1.7.4.4 In-reply-to: <1351230570-21597-1-git-send-email-rajeshwari.s@samsung.com> References: <1351230570-21597-1-git-send-email-rajeshwari.s@samsung.com> DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrALMWRmVeSWpSXmKPExsWyRsSkRnerSleAwZQ2ZouH62+yWEw5/IXF gcnjzrU9bAGMUVw2Kak5mWWpRfp2CVwZ3/dMZyn4ZlyxZN9j5gbGd1pdjBwcEgImEjeXCHcx cgKZYhIX7q1n62Lk4hASWMooMf/NNWaIhInE29dPoRKLGCVO/WxnhXAmMkn8/nsarIpNwEhi 68lpjCC2iICExK/+q4wgG5gFSiWmTMwDCQsLGEr8/7KSHcRmEVCV6O3+ywJi8wp4SOx++psF YpmCxLGpX1lBbE4BT4lLf34ygdhCQDWLz+1lgugVkPg2+RALxAOyEpsOMIOcIyFwn03iWOcc Nog5khIHV9xgmcAovICRYRWjaGpBckFxUnquoV5xYm5xaV66XnJ+7iZGYDCe/vdMagfjygaL Q4wCHIxKPLwRKZ0BQqyJZcWVuYcYJTiYlUR4d08FCvGmJFZWpRblxxeV5qQWH2L0AbpkIrOU aHI+MFLySuINjU3MTY1NLY2MzExNcQgrifM2e6QECAmkJ5akZqemFqQWwYxj4uCUamAMfxLu Ulz0L1+6wlnnwQGhbScXVn8qvSH/PNtqrX7L/AKXfQZOv9N9ahamJV36r2JX1toTNNt5rkrm +8j97b1rn9iJCjhFW+/u9EqZ9STL9r73Icf5BWyLzDJbPvFn1fi+3/d7wZaAN3vbJqzgv6nv z6lpbvbtI9sF7w28DE+0f04tNtu/o02JpTgj0VCLuag4EQC2MYM0cwIAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRmVeSWpSXmKPExsVy+t9jAd0tKl0BBtM3G1o8XH+TxWLK4S8s Dkwed67tYQtgjGpgtMlITUxJLVJIzUvOT8nMS7dV8g6Od443NTMw1DW0tDBXUshLzE21VXLx CdB1y8wBmq2kUJaYUwoUCkgsLlbSt8M0ITTETdcCpjFC1zckCK7HyAANJKxhzPi+ZzpLwTfj iiX7HjM3ML7T6mLk5JAQMJF4+/opG4QtJnHh3nogm4tDSGARo8Spn+2sEM5EJonff08zg1Sx CRhJbD05jRHEFhGQkPjVfxXI5uBgFiiVmDIxDyQsLGAo8f/LSnYQm0VAVaK3+y8LiM0r4CGx ++lvFohlChLHpn5lBbE5BTwlLv35yQRiCwHVLD63l2kCI+8CRoZVjKKpBckFxUnpuYZ6xYm5 xaV56XrJ+bmbGMHB/kxqB+PKBotDjAIcjEo8vBEpnQFCrIllxZW5hxglOJiVRHh3TwUK8aYk VlalFuXHF5XmpBYfYvQBumois5Rocj4wEvNK4g2NTcxNjU0tTSxMzCxxCCuJ8zZ7pAQICaQn lqRmp6YWpBbBjGPi4JRqYFzQ/fMtj7JJ3v7TdS96qx9tWzSP31fF5IXiqgdhl43sLFb/cPu4 bY1RYvLTNw6Wi9y9d6+rtf24Jn1hcXbUXrWde5kfudya4H9ZlUPuoLp3i9bhy46FHLd2GxW1 ch6ONT/wQviHQ7g9Y3XN64WTrs5/7t/E97lT6fGhnuwpj5Y86f6rlszRtFSJpTgj0VCLuag4 EQBOi7lCowIAAA== X-CFilter-Loop: Reflected X-Gm-Message-State: ALoCoQk4JSpDGrUoY7IlpY0nmdwj68A4ibrctqfOPEVVr3bwCLAnpmPaHtoFbIG3LF+Kr1uZB907 This patch adds clock support for I2S Signed-off-by: R. Chandrasekar Signed-off-by: Rajeshwari Shinde Acked-by: Simon Glass --- Changes in V2: - None Changes in V3: - Changes clock function names as suggested by Minkyu Kang. Changes in V4: - None arch/arm/cpu/armv7/exynos/clock.c | 120 ++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 3 + arch/arm/include/asm/arch-exynos/clock.h | 29 +++++++ 3 files changed, 152 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 4f3b451..5f7d884 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -26,6 +26,16 @@ #include #include +/* Epll Clock division values to achive different frequency output */ +static struct set_epll_con_val exynos5_epll_div[] = { + { 192000000, 0, 48, 3, 1, 0 }, + { 180000000, 0, 45, 3, 1, 0 }, + { 73728000, 1, 73, 3, 3, 47710 }, + { 67737600, 1, 90, 4, 3, 20762 }, + { 49152000, 0, 49, 3, 3, 9961 }, + { 45158400, 0, 45, 3, 3, 10381 }, + { 180633600, 0, 45, 3, 1, 10381 } +}; /* exynos4: return pll clock frequency */ static unsigned long exynos4_get_pll_clk(int pllreg) { @@ -732,6 +742,93 @@ static unsigned long exynos5_get_i2c_clk(void) return aclk_66; } +int exynos5_set_epll_clk(unsigned long rate) +{ + unsigned int epll_con, epll_con_k; + unsigned int i; + unsigned int lockcnt; + unsigned int start; + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + epll_con = readl(&clk->epll_con0); + epll_con &= ~((EPLL_CON0_LOCK_DET_EN_MASK << + EPLL_CON0_LOCK_DET_EN_SHIFT) | + EPLL_CON0_MDIV_MASK << EPLL_CON0_MDIV_SHIFT | + EPLL_CON0_PDIV_MASK << EPLL_CON0_PDIV_SHIFT | + EPLL_CON0_SDIV_MASK << EPLL_CON0_SDIV_SHIFT); + + for (i = 0; i < ARRAY_SIZE(exynos5_epll_div); i++) { + if (exynos5_epll_div[i].freq_out == rate) + break; + } + + if (i == ARRAY_SIZE(exynos5_epll_div)) + return -1; + + epll_con_k = exynos5_epll_div[i].k_dsm << 0; + epll_con |= exynos5_epll_div[i].en_lock_det << + EPLL_CON0_LOCK_DET_EN_SHIFT; + epll_con |= exynos5_epll_div[i].m_div << EPLL_CON0_MDIV_SHIFT; + epll_con |= exynos5_epll_div[i].p_div << EPLL_CON0_PDIV_SHIFT; + epll_con |= exynos5_epll_div[i].s_div << EPLL_CON0_SDIV_SHIFT; + + /* + * Required period ( in cycles) to genarate a stable clock output. + * The maximum clock time can be up to 3000 * PDIV cycles of PLLs + * frequency input (as per spec) + */ + lockcnt = 3000 * exynos5_epll_div[i].p_div; + + writel(lockcnt, &clk->epll_lock); + writel(epll_con, &clk->epll_con0); + writel(epll_con_k, &clk->epll_con1); + + start = get_timer(0); + + while (!(readl(&clk->epll_con0) & + (0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT))) { + if (get_timer(start) > TIMEOUT_EPLL_LOCK) { + debug("%s: Timeout waiting for EPLL lock\n", __func__); + return -1; + } + } + return 0; +} + +void exynos5_set_i2s_clk_source(void) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + + clrsetbits_le32(&clk->src_peric1, AUDIO1_SEL_MASK, + (CLK_SRC_SCLK_EPLL)); +} + +int exynos5_set_i2s_clk_prescaler(unsigned int src_frq, + unsigned int dst_frq) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + unsigned int div; + + if ((dst_frq == 0) || (src_frq == 0)) { + debug("%s: Invalid requency input for prescaler\n", __func__); + debug("src frq = %d des frq = %d ", src_frq, dst_frq); + return -1; + } + + div = (src_frq / dst_frq); + if (div > AUDIO_1_RATIO_MASK) { + debug("%s: Frequency ratio is out of range\n", __func__); + debug("src frq = %d des frq = %d ", src_frq, dst_frq); + return -1; + } + clrsetbits_le32(&clk->div_peric4, AUDIO_1_RATIO_MASK, + (div & AUDIO_1_RATIO_MASK)); + return 0; +} + unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) @@ -803,3 +900,26 @@ void set_mipi_clk(void) if (cpu_is_exynos4()) exynos4_set_mipi_clk(); } + +int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq) +{ + + if (cpu_is_exynos5()) + return exynos5_set_i2s_clk_prescaler(src_frq, dst_frq); + else + return 0; +} + +void set_i2s_clk_source(void) +{ + if (cpu_is_exynos5()) + exynos5_set_i2s_clk_source(); +} + +int set_epll_clk(unsigned long rate) +{ + if (cpu_is_exynos5()) + return exynos5_set_epll_clk(rate); + else + return 0; +} diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 5529025..2bf2c10 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -38,5 +38,8 @@ void set_mmc_clk(int dev_index, unsigned int div); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void); +void set_i2s_clk_source(void); +int set_i2s_clk_prescaler(unsigned int src_frq, unsigned int dst_frq); +int set_epll_clk(unsigned long rate); #endif diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h index fce38ef..ff6781a 100644 --- a/arch/arm/include/asm/arch-exynos/clock.h +++ b/arch/arm/include/asm/arch-exynos/clock.h @@ -595,9 +595,38 @@ struct exynos5_clock { unsigned int pll_div2_sel; unsigned char res123[0xf5d8]; }; + +/* structure for epll configuration used in audio clock configuration */ +struct set_epll_con_val { + unsigned int freq_out; /* frequency out */ + unsigned int en_lock_det; /* enable lock detect */ + unsigned int m_div; /* m divider value */ + unsigned int p_div; /* p divider value */ + unsigned int s_div; /* s divider value */ + unsigned int k_dsm; /* k value of delta signal modulator */ +}; #endif #define MPLL_FOUT_SEL_SHIFT 4 +#define EXYNOS5_EPLLCON0_LOCKED_SHIFT 29 /* EPLL Locked bit position*/ +#define TIMEOUT_EPLL_LOCK 1000 + +#define AUDIO_0_RATIO_MASK 0x0f +#define AUDIO_1_RATIO_MASK 0x0f + +#define AUDIO1_SEL_MASK 0xf +#define CLK_SRC_SCLK_EPLL 0x7 + +/* CON0 bit-fields */ +#define EPLL_CON0_MDIV_MASK 0x1ff +#define EPLL_CON0_PDIV_MASK 0x3f +#define EPLL_CON0_SDIV_MASK 0x7 +#define EPLL_CON0_MDIV_SHIFT 16 +#define EPLL_CON0_PDIV_SHIFT 8 +#define EPLL_CON0_SDIV_SHIFT 0 +#define EPLL_CON0_LOCK_DET_EN_SHIFT 28 +#define EPLL_CON0_LOCK_DET_EN_MASK 1 + #define MPLL_FOUT_SEL_MASK 0x1 #define BPLL_FOUT_SEL_SHIFT 0 #define BPLL_FOUT_SEL_MASK 0x1