From patchwork Mon Feb 3 21:02:59 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Darwin Rambo X-Patchwork-Id: 24066 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-qc0-f199.google.com (mail-qc0-f199.google.com [209.85.216.199]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id A76E120341 for ; Mon, 3 Feb 2014 21:04:49 +0000 (UTC) Received: by mail-qc0-f199.google.com with SMTP id m20sf19146848qcx.2 for ; Mon, 03 Feb 2014 13:04:48 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-archive:list-post:list-help:list-subscribe :sender:errors-to:x-original-sender :x-original-authentication-results:mailing-list:content-type :content-transfer-encoding; bh=N5ciY1E7EokaSJXLu5NAGYrep6tOf7Ky+mVLUzK5hy4=; b=hPBbjJ1JuHo17OnATct5JMP7RA9ALBE+ZVRoBdvhhDnkyKbv5GQwaM2qcDH5iIm9nC qS1l48sqiefM5Y4eCTNZz9Qwx38hg22bnm28bLZrG2VLWqFlXBhmyfNRuvcSzWvhpGCO QRikACgXL6q3lPtqSkLSn2K2hcZcEWdD7CKNhksCmiGv7AB1hkbD2zq/EEPvzz/i33Rx 2g11K7PIDF28iTY4BsyfWOAeedw201mAo/AEkTZx2mCh11AEfDEWt9O5girCoMfVxd5d ELFvWGGaoRl5gxOT5CLjepnB/ZjZr3AZKm9BguFP2s/qxTztYxVMBhyphLHTqAMaTNxK Y09g== X-Gm-Message-State: ALoCoQnHTLcYk9EJACZYszp4bvZctLkV6Qj5WpPooU0qFBuXEYya1Wno4NhDbKF1CZxpH404Odk/ X-Received: by 10.236.86.77 with SMTP id v53mr13296492yhe.41.1391461488816; Mon, 03 Feb 2014 13:04:48 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.29.102 with SMTP id a93ls1953304qga.33.gmail; Mon, 03 Feb 2014 13:04:48 -0800 (PST) X-Received: by 10.58.235.129 with SMTP id um1mr30898887vec.17.1391461488709; Mon, 03 Feb 2014 13:04:48 -0800 (PST) Received: from mail-ve0-f170.google.com (mail-ve0-f170.google.com [209.85.128.170]) by mx.google.com with ESMTPS id yv5si7168591veb.102.2014.02.03.13.04.48 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Mon, 03 Feb 2014 13:04:48 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.170; Received: by mail-ve0-f170.google.com with SMTP id cz12so5504389veb.1 for ; Mon, 03 Feb 2014 13:04:48 -0800 (PST) X-Received: by 10.52.104.68 with SMTP id gc4mr24973864vdb.2.1391461488615; Mon, 03 Feb 2014 13:04:48 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.174.196 with SMTP id u4csp183932vcz; Mon, 3 Feb 2014 13:04:47 -0800 (PST) X-Received: by 10.15.99.201 with SMTP id bl49mr10586555eeb.53.1391461487332; Mon, 03 Feb 2014 13:04:47 -0800 (PST) Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id k3si37776291eep.162.2014.02.03.13.04.46 for ; Mon, 03 Feb 2014 13:04:47 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 58C344B87D; Mon, 3 Feb 2014 22:04:46 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id O0vRLeERpTcn; Mon, 3 Feb 2014 22:04:46 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id DBA7A4B898; Mon, 3 Feb 2014 22:04:39 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CB9AB4B898 for ; Mon, 3 Feb 2014 22:04:37 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ey8ffz5ier8W for ; Mon, 3 Feb 2014 22:04:36 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-gw2-out.broadcom.com (mail-gw2-out.broadcom.com [216.31.210.63]) by theia.denx.de (Postfix) with ESMTP id 491444B89A for ; Mon, 3 Feb 2014 22:03:56 +0100 (CET) X-IronPort-AV: E=Sophos;i="4.95,774,1384329600"; d="scan'208";a="12746716" Received: from irvexchcas08.broadcom.com (HELO IRVEXCHCAS08.corp.ad.broadcom.com) ([10.9.208.57]) by mail-gw2-out.broadcom.com with ESMTP; 03 Feb 2014 13:17:03 -0800 Received: from IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.3.174.1; Mon, 3 Feb 2014 13:03:55 -0800 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) with Microsoft SMTP Server id 14.3.174.1; Mon, 3 Feb 2014 13:03:54 -0800 Received: from mail.broadcom.com (dhcp-rmna-vpn-108.ric.broadcom.com [10.136.253.108]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 9E7A5246A3; Mon, 3 Feb 2014 13:03:54 -0800 (PST) From: Darwin Rambo To: Date: Mon, 3 Feb 2014 13:02:59 -0800 Message-ID: <1391461382-24986-4-git-send-email-drambo@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1391461382-24986-1-git-send-email-drambo@broadcom.com> References: <1391461382-24986-1-git-send-email-drambo@broadcom.com> MIME-Version: 1.0 Cc: Darwin Rambo Subject: [U-Boot] [PATCH v1 3/6] gpio: kona: Add Kona gpio driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: drambo@broadcom.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.170 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Add support for the Kona GPIO controller found on Broadcom mobile SoCs. Signed-off-by: Darwin Rambo Reviewed-by: Steve Rae Reviewed-by: Markus Mayer Reviewed-by: Tim Kryger --- drivers/gpio/Makefile | 1 + drivers/gpio/kona_gpio.c | 141 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 142 insertions(+) create mode 100644 drivers/gpio/kona_gpio.c diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index b903c45..ed2c0c7 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_AT91_GPIO) += at91_gpio.o obj-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o obj-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o +obj-$(CONFIG_KONA_GPIO) += kona_gpio.o obj-$(CONFIG_MARVELL_GPIO) += mvgpio.o obj-$(CONFIG_MARVELL_MFP) += mvmfp.o obj-$(CONFIG_MXC_GPIO) += mxc_gpio.o diff --git a/drivers/gpio/kona_gpio.c b/drivers/gpio/kona_gpio.c new file mode 100644 index 0000000..ce0e499 --- /dev/null +++ b/drivers/gpio/kona_gpio.c @@ -0,0 +1,141 @@ +/* + * Copyright 2013 Broadcom Corporation. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define GPIO_BASE (void *)GPIO2_BASE_ADDR + +#define GPIO_PASSWD 0x00a5a501 +#define GPIO_PER_BANK 32 +#define GPIO_MAX_BANK_NUM 8 + +#define GPIO_BANK(gpio) ((gpio) >> 5) +#define GPIO_BITMASK(gpio) \ + (1UL << ((gpio) & (GPIO_PER_BANK - 1))) + +#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) +#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) +#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) +#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) +#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) +#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) +#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) +#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) +#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) + +#define GPIO_GPPWR_OFFSET 0x00000520 + +#define GPIO_GPCTR0_DBR_SHIFT 5 +#define GPIO_GPCTR0_DBR_MASK 0x000001e0 + +#define GPIO_GPCTR0_ITR_SHIFT 3 +#define GPIO_GPCTR0_ITR_MASK 0x00000018 +#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 +#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 +#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 + +#define GPIO_GPCTR0_IOTR_MASK 0x00000001 +#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 +#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 + +int gpio_request(unsigned gpio, const char *label) +{ + unsigned int value, off; + + writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); + off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); + value = readl(GPIO_BASE + off) & ~GPIO_BITMASK(gpio); + writel(value, GPIO_BASE + off); + + return 0; +} + +int gpio_free(unsigned gpio) +{ + unsigned int value, off; + + writel(GPIO_PASSWD, GPIO_BASE + GPIO_GPPWR_OFFSET); + off = GPIO_PWD_STATUS(GPIO_BANK(gpio)); + value = readl(GPIO_BASE + off) | GPIO_BITMASK(gpio); + writel(value, GPIO_BASE + off); + + return 0; +} + +int gpio_direction_input(unsigned gpio) +{ + u32 val; + + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= ~GPIO_GPCTR0_IOTR_MASK; + val |= GPIO_GPCTR0_IOTR_CMD_INPUT; + writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); + + return 0; +} + +int gpio_direction_output(unsigned gpio, int value) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= ~GPIO_GPCTR0_IOTR_MASK; + val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; + writel(val, GPIO_BASE + GPIO_CONTROL(gpio)); + off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); + + val = readl(GPIO_BASE + off); + val |= bitmask; + writel(val, GPIO_BASE + off); + + return 0; +} + +int gpio_get_value(unsigned gpio) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + /* determine the GPIO pin direction */ + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= GPIO_GPCTR0_IOTR_MASK; + + /* read the GPIO bank status */ + off = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ? + GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id); + val = readl(GPIO_BASE + off); + + /* return the specified bit status */ + return !!(val & bitmask); +} + +void gpio_set_value(unsigned gpio, int value) +{ + int bank_id = GPIO_BANK(gpio); + int bitmask = GPIO_BITMASK(gpio); + u32 val, off; + + /* determine the GPIO pin direction */ + val = readl(GPIO_BASE + GPIO_CONTROL(gpio)); + val &= GPIO_GPCTR0_IOTR_MASK; + + /* this function only applies to output pin */ + if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) { + printf("%s: Cannot set an input pin %d\n", __func__, gpio); + return; + } + + off = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); + + val = readl(GPIO_BASE + off); + val |= bitmask; + writel(val, GPIO_BASE + off); +}