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[85.214.87.163]) by mx.google.com with ESMTP id k3si18575356eep.183.2014.02.15.06.13.04 for ; Sat, 15 Feb 2014 06:13:05 -0800 (PST) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E984C4B778; Sat, 15 Feb 2014 15:12:48 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id v2OAMl8PS+xF; Sat, 15 Feb 2014 15:12:48 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 34EAA4B72C; Sat, 15 Feb 2014 15:11:54 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 724634B768 for ; Sat, 15 Feb 2014 15:11:39 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id AsXOMpLuetiD for ; Sat, 15 Feb 2014 15:11:39 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from inca-roads.misterjones.org (inca-roads.misterjones.org [213.251.177.50]) by theia.denx.de (Postfix) with ESMTPS id 0D8344B70D for ; Sat, 15 Feb 2014 15:11:21 +0100 (CET) Received: from [176.250.132.24] (helo=why.wild-wind.fr.eu.org) by cheepnis.misterjones.org with esmtpsa (TLS1.2:RSA_AES_128_CBC_SHA256:128) (Exim 4.80) (envelope-from ) id 1WEfQK-00038M-Qy; Sat, 15 Feb 2014 14:36:52 +0100 From: Marc Zyngier To: u-boot@lists.denx.de, linux-sunxi@googlegroups.com Date: Sat, 15 Feb 2014 13:36:32 +0000 Message-Id: <1392471397-2158-9-git-send-email-marc.zyngier@arm.com> X-Mailer: git-send-email 1.8.5.1 In-Reply-To: <1392471397-2158-1-git-send-email-marc.zyngier@arm.com> References: <1392471397-2158-1-git-send-email-marc.zyngier@arm.com> X-SA-Exim-Connect-IP: 176.250.132.24 X-SA-Exim-Rcpt-To: u-boot@lists.denx.de, linux-sunxi@googlegroups.com, maxime.ripard@free-electrons.com, ijc@hellion.org.uk, andre@andrep.de, henrik@henriknordstrom.net, maz@misterjones.org X-SA-Exim-Mail-From: marc.zyngier@arm.com X-SA-Exim-Scanned: No (on cheepnis.misterjones.org); SAEximRunCond expanded to false Cc: Andre Przywara , maz@misterjones.org, Ian Campbell Subject: [U-Boot] [PATCH v3 08/13] ARM: HYP/non-sec: add the option for a second-stage monitor X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: marc.zyngier@arm.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.175 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Allow the switch to a second stage secure monitor just before switching to non-secure. This allows a resident piece of firmware to be active once the kernel has been entered (the u-boot monitor is dead anyway, its pages being reused). Signed-off-by: Marc Zyngier --- arch/arm/cpu/armv7/nonsec_virt.S | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S index 2a43e3c..745670e 100644 --- a/arch/arm/cpu/armv7/nonsec_virt.S +++ b/arch/arm/cpu/armv7/nonsec_virt.S @@ -44,10 +44,19 @@ _monitor_vectors: * ip: target PC */ _secure_monitor: +#ifdef CONFIG_ARMV7_PSCI + ldr r5, =_psci_vectors @ Switch to the next monitor + mcr p15, 0, r5, c12, c0, 1 + isb + + @ Obtain a secure stack, and configure the PSCI backend + bl psci_arch_init +#endif + mrc p15, 0, r5, c1, c1, 0 @ read SCR - bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits + bic r5, r5, #0x4a @ clear IRQ, EA, nET bits orr r5, r5, #0x31 @ enable NS, AW, FW bits - + @ FIQ preserved for secure mode mov r6, #SVC_MODE @ default mode is SVC is_cpu_virt_capable r4 #ifdef CONFIG_ARMV7_VIRT