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[85.214.87.163]) by mx.google.com with ESMTP id fr17si6326334wjc.2.2015.10.01.02.48.53; Thu, 01 Oct 2015 02:48:53 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CEE464B8A5; Thu, 1 Oct 2015 11:48:47 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ykR3pUNEq_Zv; Thu, 1 Oct 2015 11:48:47 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7B2D14B882; Thu, 1 Oct 2015 11:48:47 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C80784B882 for ; Thu, 1 Oct 2015 11:48:44 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id DXQ8PruhYJXc for ; Thu, 1 Oct 2015 11:48:44 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 IX_MANITU=ERR(0) (only DNSBL check requested) Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [93.93.135.160]) by theia.denx.de (Postfix) with ESMTPS id 8A8F64B807 for ; Thu, 1 Oct 2015 11:48:27 +0200 (CEST) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sjoerd) with ESMTPSA id 8630B6092C1 Received: by dusk.luon.net (Postfix, from userid 1000) id 98A53229BD; Thu, 1 Oct 2015 11:48:13 +0200 (CEST) From: Sjoerd Simons To: Simon Glass Date: Thu, 1 Oct 2015 11:48:05 +0200 Message-Id: <1443692893-19905-3-git-send-email-sjoerd.simons@collabora.co.uk> X-Mailer: git-send-email 2.5.3 In-Reply-To: <1443692893-19905-1-git-send-email-sjoerd.simons@collabora.co.uk> References: <1443692893-19905-1-git-send-email-sjoerd.simons@collabora.co.uk> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 02/10] rockchip: rk3288: Add clock support for the gmac ethernet interface X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: sjoerd.simons@collabora.co.uk X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.41 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 Setup the clocks for the gmac ethernet interface. This assumes the mac clock is fed by an external clock which is common on RK3288 based devices. Signed-off-by: Sjoerd Simons Acked-by: Simon Glass --- arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 17 +++++++++++++++++ drivers/clk/clk_rk3288.c | 16 ++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h index 7ebcc40..69ec168 100644 --- a/arch/arm/include/asm/arch-rockchip/cru_rk3288.h +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3288.h @@ -90,6 +90,23 @@ enum { SDIO0_DIV_MASK = 0x3f, }; +/* CRU_CLKSEL21_CON */ +enum { + MAC_DIV_CON_SHIFT = 0xf, + MAC_DIV_CON_MASK = 0x1f, + + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = 1, + RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, + RMII_EXTCLK_SELECT_EXT_CLK = 1, + + EMAC_PLL_SHIFT = 0, + EMAC_PLL_MASK = 0x3, + EMAC_PLL_SELECT_NEW = 0x0, + EMAC_PLL_SELECT_CODEC = 0x1, + EMAC_PLL_SELECT_GENERAL = 0x2, +}; + /* CRU_CLKSEL25_CON */ enum { SPI1_PLL_SHIFT = 0xf, diff --git a/drivers/clk/clk_rk3288.c b/drivers/clk/clk_rk3288.c index 54d4930..22f53d9 100644 --- a/drivers/clk/clk_rk3288.c +++ b/drivers/clk/clk_rk3288.c @@ -442,6 +442,18 @@ static ulong rockchip_mmc_set_clk(struct rk3288_cru *cru, uint clk_general_rate, return rockchip_mmc_get_clk(cru, clk_general_rate, periph); } +static ulong rockchip_gmac_set_clk(struct rk3288_cru *cru, + uint clk_general_rate, + enum periph_id periph, uint freq) +{ + /* Assuming mac_clk is fed by an external clock */ + rk_clrsetreg(&cru->cru_clksel_con[21], + RMII_EXTCLK_MASK << RMII_EXTCLK_SHIFT, + RMII_EXTCLK_SELECT_EXT_CLK << RMII_EXTCLK_SHIFT); + + return 0; +} + static ulong rockchip_spi_get_clk(struct rk3288_cru *cru, uint clk_general_rate, enum periph_id periph) { @@ -514,6 +526,10 @@ ulong rk3288_set_periph_rate(struct udevice *dev, int periph, ulong rate) ulong new_rate; switch (periph) { + case PERIPH_ID_GMAC: + new_rate = rockchip_gmac_set_clk(priv->cru, clk_get_rate(dev), + periph, rate); + break; case PERIPH_ID_EMMC: case PERIPH_ID_SDCARD: new_rate = rockchip_mmc_set_clk(priv->cru, clk_get_rate(dev),