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[85.214.87.163]) by mx.google.com with ESMTP id 131si75894wmg.123.2016.03.15.16.10.30; Tue, 15 Mar 2016 16:10:30 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A8C75A7693; Wed, 16 Mar 2016 00:09:50 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VwozUoox6vwf; Wed, 16 Mar 2016 00:09:50 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B08D2A7696; Wed, 16 Mar 2016 00:09:40 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D9F48A75B9 for ; Wed, 16 Mar 2016 00:09:26 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2DaUxaHZQfPx for ; Wed, 16 Mar 2016 00:09:26 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 2D409A75C2 for ; Wed, 16 Mar 2016 00:09:21 +0100 (CET) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u2FN9IUf008199; Tue, 15 Mar 2016 18:09:18 -0500 Received: from DLEE71.ent.ti.com (dlee71.ent.ti.com [157.170.170.114]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2FN9IZQ010619; Tue, 15 Mar 2016 18:09:18 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE71.ent.ti.com (157.170.170.114) with Microsoft SMTP Server id 14.3.224.2; Tue, 15 Mar 2016 18:09:18 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2FN9It8028349; Tue, 15 Mar 2016 18:09:18 -0500 From: Nishanth Menon To: Tom Rini Date: Tue, 15 Mar 2016 18:09:13 -0500 Message-ID: <1458083357-31509-4-git-send-email-nm@ti.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1458083357-31509-1-git-send-email-nm@ti.com> References: <1458083357-31509-1-git-send-email-nm@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de, Vishal Mahaveer Subject: [U-Boot] [PATCH 3/7] ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Based on data from EMIF configuration tool 1.1.1. Signed-off-by: Nishanth Menon --- arch/arm/cpu/armv7/omap5/sdram.c | 44 +++++++++++++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) -- 1.7.9.5 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 5cf360c41468..7712923d8572 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -398,6 +398,45 @@ dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = { 0x0 }; +const u32 dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2[] = { + 0x04040100, + 0x006B009F, + 0x006B00A2, + 0x006B00A8, + 0x006B00A8, + 0x006B00B2, + 0x002F002F, + 0x002F002F, + 0x002F002F, + 0x002F002F, + 0x002F002F, + 0x00600073, + 0x00600071, + 0x0060007C, + 0x0060007E, + 0x00600084, + 0x00400053, + 0x00400051, + 0x0040005C, + 0x0040005E, + 0x00400064, + 0x00800080, + 0x00800080, + 0x40010080, + 0x08102040, + 0x005B008F, + 0x005B0092, + 0x005B0098, + 0x005B0098, + 0x005B00A2, + 0x00300043, + 0x00300041, + 0x0030004C, + 0x0030004E, + 0x00300054, + 0x00000077 +}; + const struct lpddr2_mr_regs mr_regs = { .mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8, .mr2 = 0x6, @@ -438,10 +477,13 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, } break; case DRA722_ES1_0: - case DRA722_ES2_0: *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz; *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz); break; + case DRA722_ES2_0: + *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2; + *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2); + break; default: *regs = ddr3_ext_phy_ctrl_const_base_es2; *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);