From patchwork Thu Mar 24 13:32:44 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 64362 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp649373lbc; Thu, 24 Mar 2016 06:34:19 -0700 (PDT) X-Received: by 10.28.17.141 with SMTP id 135mr11159137wmr.48.1458826459573; Thu, 24 Mar 2016 06:34:19 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id ha10si9080820wjc.117.2016.03.24.06.34.19; Thu, 24 Mar 2016 06:34:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 384A6A7679; Thu, 24 Mar 2016 14:33:27 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id T7Of0swul7Tf; Thu, 24 Mar 2016 14:33:27 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6EA15A7498; Thu, 24 Mar 2016 14:33:11 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 278A9A74C5 for ; Thu, 24 Mar 2016 14:32:25 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id OVrDygAvPnDo for ; Thu, 24 Mar 2016 14:32:25 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg010-v.nifty.com (conuserg010.nifty.com [202.248.44.36]) by theia.denx.de (Postfix) with ESMTPS id 17378A7532 for ; Thu, 24 Mar 2016 14:32:19 +0100 (CET) Received: from beagle.diag.org (p14090-ipngnfx01kyoto.kyoto.ocn.ne.jp [153.142.97.90]) (authenticated) by conuserg010-v.nifty.com with ESMTP id u2ODW5nL018160; Thu, 24 Mar 2016 22:32:09 +0900 X-Nifty-SrcIP: [153.142.97.90] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 24 Mar 2016 22:32:44 +0900 Message-Id: <1458826368-2159-8-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1458826368-2159-1-git-send-email-yamada.masahiro@socionext.com> References: <1458826368-2159-1-git-send-email-yamada.masahiro@socionext.com> Subject: [U-Boot] [PATCH 07/10] pinctrl: uniphier: introduce quirks flags X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The core part of the UniPhier pinctrl driver needs to support a new quirk for upcoming UniPhier ARMv8 SoCs. This often happens because pinctrl drivers include really SoC-specific stuff. This commit intends to tidy up SoC-specific parameters of the existing drivers before adding new ones. Having flags would be better than adding new members every time a new SoC-specific quirk comes up. At this time, there is one flag, UNIPHIER_PINCTRL_DBGMUX_SEPARATE. This quirk was added for PH1-Pro4 and PH1-Pro5 as requirement from our customer. For those SoCs, one pinmux setting is controlled by the combination of two separate registers; LSB bits at register offset (8 * N) and MSB bits at (8 * N + 4). Because it is impossible to update two separate registers atomically, the LOAD_PINCTRL register should be set in order to make the pinmux settings really effective. Signed-off-by: Masahiro Yamada --- drivers/pinctrl/uniphier/pinctrl-uniphier-core.c | 27 ++++++++++++++++++++---- drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c | 3 --- drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c | 3 --- drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c | 4 +--- drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c | 4 +--- drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c | 3 --- drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c | 3 --- drivers/pinctrl/uniphier/pinctrl-uniphier.h | 8 +++---- 8 files changed, 28 insertions(+), 27 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c index ac3a06c..7a6c95c 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-core.c @@ -68,14 +68,33 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, unsigned muxval) { struct uniphier_pinctrl_priv *priv = dev_get_priv(dev); - unsigned mux_bits = priv->socdata->mux_bits; - unsigned reg_stride = priv->socdata->reg_stride; - unsigned reg, reg_end, shift, mask; + unsigned mux_bits, reg_stride, reg, reg_end, shift, mask; + bool load_pinctrl; u32 tmp; /* some pins need input-enabling */ uniphier_pinconf_input_enable(dev, pin); + if (priv->socdata->quirks & UNIPHIER_PINCTRL_DBGMUX_SEPARATE) { + /* + * Mode offset bit + * Normal 4 * n shift+3:shift + * Debug 4 * n shift+7:shift+4 + */ + mux_bits = 4; + reg_stride = 8; + load_pinctrl = true; + } else { + /* + * Mode offset bit + * Normal 8 * n shift+3:shift + * Debug 8 * n + 4 shift+3:shift + */ + mux_bits = 8; + reg_stride = 4; + load_pinctrl = false; + } + reg = UNIPHIER_PINCTRL_PINMUX_BASE + pin * mux_bits / 32 * reg_stride; reg_end = reg + reg_stride; shift = pin * mux_bits % 32; @@ -94,7 +113,7 @@ static void uniphier_pinmux_set_one(struct udevice *dev, unsigned pin, muxval >>= mux_bits; } - if (priv->socdata->load_pinctrl) + if (load_pinctrl) writel(1, priv->base + UNIPHIER_PINCTRL_LOAD_PINMUX); } diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c index b3d47f0..8f7574e 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld4.c @@ -107,9 +107,6 @@ static struct uniphier_pinctrl_socdata ph1_ld4_pinctrl_socdata = { .groups_count = ARRAY_SIZE(ph1_ld4_groups), .functions = ph1_ld4_functions, .functions_count = ARRAY_SIZE(ph1_ld4_functions), - .mux_bits = 8, - .reg_stride = 4, - .load_pinctrl = false, }; static int ph1_ld4_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c index 8703a21..2a5d5f3 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-ld6b.c @@ -107,9 +107,6 @@ static struct uniphier_pinctrl_socdata ph1_ld6b_pinctrl_socdata = { .groups_count = ARRAY_SIZE(ph1_ld6b_groups), .functions = ph1_ld6b_functions, .functions_count = ARRAY_SIZE(ph1_ld6b_functions), - .mux_bits = 8, - .reg_stride = 4, - .load_pinctrl = false, }; static int ph1_ld6b_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c index b3eaf13..e07fafb 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro4.c @@ -103,9 +103,7 @@ static struct uniphier_pinctrl_socdata ph1_pro4_pinctrl_socdata = { .groups_count = ARRAY_SIZE(ph1_pro4_groups), .functions = ph1_pro4_functions, .functions_count = ARRAY_SIZE(ph1_pro4_functions), - .mux_bits = 4, - .reg_stride = 8, - .load_pinctrl = true, + .quirks = UNIPHIER_PINCTRL_DBGMUX_SEPARATE, }; static int ph1_pro4_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c index 3749250..d20db9f 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pro5.c @@ -117,9 +117,7 @@ static struct uniphier_pinctrl_socdata ph1_pro5_pinctrl_socdata = { .groups_count = ARRAY_SIZE(ph1_pro5_groups), .functions = ph1_pro5_functions, .functions_count = ARRAY_SIZE(ph1_pro5_functions), - .mux_bits = 4, - .reg_stride = 8, - .load_pinctrl = true, + .quirks = UNIPHIER_PINCTRL_DBGMUX_SEPARATE, }; static int ph1_pro5_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c index 2cca69d..976bb2f 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-pxs2.c @@ -114,9 +114,6 @@ static struct uniphier_pinctrl_socdata proxstream2_pinctrl_socdata = { .groups_count = ARRAY_SIZE(proxstream2_groups), .functions = proxstream2_functions, .functions_count = ARRAY_SIZE(proxstream2_functions), - .mux_bits = 8, - .reg_stride = 4, - .load_pinctrl = false, }; static int proxstream2_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c index 5fafdb6..6cbf215 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier-sld8.c @@ -115,9 +115,6 @@ static struct uniphier_pinctrl_socdata ph1_sld8_pinctrl_socdata = { .groups_count = ARRAY_SIZE(ph1_sld8_groups), .functions = ph1_sld8_functions, .functions_count = ARRAY_SIZE(ph1_sld8_functions), - .mux_bits = 8, - .reg_stride = 4, - .load_pinctrl = false, }; static int ph1_sld8_pinctrl_probe(struct udevice *dev) diff --git a/drivers/pinctrl/uniphier/pinctrl-uniphier.h b/drivers/pinctrl/uniphier/pinctrl-uniphier.h index 6bdebf2..e622d93 100644 --- a/drivers/pinctrl/uniphier/pinctrl-uniphier.h +++ b/drivers/pinctrl/uniphier/pinctrl-uniphier.h @@ -59,8 +59,7 @@ struct uniphier_pinctrl_group { * @functions_count: number of pinmux functions * @mux_bits: bit width of each pinmux register * @reg_stride: stride of pinmux register address - * @load_pinctrl: if true, LOAD_PINMUX register must be set to one for new - * values in pinmux registers to become really effective + * @quirks: SoC-specific quirk flags */ struct uniphier_pinctrl_socdata { const struct uniphier_pinctrl_pin *pins; @@ -69,9 +68,8 @@ struct uniphier_pinctrl_socdata { int groups_count; const char * const *functions; int functions_count; - unsigned mux_bits; - unsigned reg_stride; - bool load_pinctrl; + unsigned quirks; +#define UNIPHIER_PINCTRL_DBGMUX_SEPARATE BIT(0) }; #define UNIPHIER_PINCTRL_PIN(a, b) \