From patchwork Thu Mar 31 12:42:39 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Murphy X-Patchwork-Id: 64776 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp133747lbc; Thu, 31 Mar 2016 05:42:52 -0700 (PDT) X-Received: by 10.28.136.211 with SMTP id k202mr31062006wmd.93.1459428172818; Thu, 31 Mar 2016 05:42:52 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id i66si6551931wmf.31.2016.03.31.05.42.52; Thu, 31 Mar 2016 05:42:52 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 91774A7498; Thu, 31 Mar 2016 14:42:51 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id eBv-Ccv_pE_Q; Thu, 31 Mar 2016 14:42:51 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 35C04A74D6; Thu, 31 Mar 2016 14:42:51 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 8E5E8A74D6 for ; Thu, 31 Mar 2016 14:42:47 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5mQlQ3pVCWO3 for ; Thu, 31 Mar 2016 14:42:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from arroyo.ext.ti.com (arroyo.ext.ti.com [192.94.94.40]) by theia.denx.de (Postfix) with ESMTPS id 14BCCA7498 for ; Thu, 31 Mar 2016 14:42:44 +0200 (CEST) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by arroyo.ext.ti.com (8.13.7/8.13.7) with ESMTP id u2VCgfmA030094; Thu, 31 Mar 2016 07:42:42 -0500 Received: from DFLE72.ent.ti.com (dfle72.ent.ti.com [128.247.5.109]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2VCgfjw012607; Thu, 31 Mar 2016 07:42:41 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DFLE72.ent.ti.com (128.247.5.109) with Microsoft SMTP Server id 14.3.224.2; Thu, 31 Mar 2016 07:42:41 -0500 Received: from legion.dal.design.ti.com (legion.dal.design.ti.com [128.247.22.53]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id u2VCgfaN027203; Thu, 31 Mar 2016 07:42:41 -0500 Received: from localhost (a0272616local.am.dhcp.ti.com [172.22.166.18]) by legion.dal.design.ti.com (8.11.7p1+Sun/8.11.7) with ESMTP id u2VCgf904967; Thu, 31 Mar 2016 07:42:41 -0500 (CDT) From: Dan Murphy To: Date: Thu, 31 Mar 2016 07:42:39 -0500 Message-ID: <1459428160-6862-1-git-send-email-dmurphy@ti.com> X-Mailer: git-send-email 2.7.2.333.g70bd996 MIME-Version: 1.0 Cc: edgar.iglesias@xilinx.com, trini@konsulko.com Subject: [U-Boot] [RFC PATCH 1/2] net: phy: ti: Allow the driver to be more configurable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Not all devices use the same internal delay or fifo depth. Add the ability to set the internal delay for rx or tx and the fifo depth via the config file. If the value is not set in the config file then set the delay to the default. Signed-off-by: Dan Murphy --- drivers/net/phy/ti.c | 71 ++++++++++++++++++++++++++++++++---- include/dt-bindings/net/ti-dp83867.h | 35 ++++++++++++++++++ 2 files changed, 98 insertions(+), 8 deletions(-) create mode 100644 include/dt-bindings/net/ti-dp83867.h -- 2.8.0.rc3 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/drivers/net/phy/ti.c b/drivers/net/phy/ti.c index c3912d5..6da0523 100644 --- a/drivers/net/phy/ti.c +++ b/drivers/net/phy/ti.c @@ -6,6 +6,9 @@ */ #include #include +#include + +#include /* TI DP83867 */ #define DP83867_DEVADDR 0x1f @@ -57,6 +60,17 @@ #define MII_MMD_CTRL_INCR_RDWT 0x8000 /* post increment on reads & writes */ #define MII_MMD_CTRL_INCR_ON_WT 0xC000 /* post increment on writes only */ +/* User setting - can be taken from DTS */ +#define DEFAULT_RX_ID_DELAY 8 +#define DEFAULT_TX_ID_DELAY 0xa +#define DEFAULT_FIFO_DEPTH 1 + +struct dp83867_private { + int rx_id_delay; + int tx_id_delay; + int fifo_depth; +}; + /** * phy_read_mmd_indirect - reads data from the MMD registers * @phydev: The PHY device bus @@ -134,16 +148,53 @@ static inline bool phy_interface_is_rgmii(struct phy_device *phydev) phydev->interface <= PHY_INTERFACE_MODE_RGMII_TXID; } -/* User setting - can be taken from DTS */ -#define RX_ID_DELAY 8 -#define TX_ID_DELAY 0xa -#define FIFO_DEPTH 1 +/** + * dp83867_data_init - Convenience function for setting PHY specific data + * @phydev: the phy_device struct + */ +static int dp83867_data_init(struct phy_device *phydev) +{ + struct dp83867_private *dp83867 = phydev->priv; + +#ifdef CONFIG_RGMII_RX_ID + dp83867->rx_id_delay = CONFIG_RGMII_RX_ID; +#else + dp83867->rx_id_delay = DEFAULT_RX_ID_DELAY; +#endif + +#ifdef CONFIG_RGMII_TX_ID + dp83867->tx_id_delay = CONFIG_RGMII_TX_ID; +#else + dp83867->tx_id_delay = DEFAULT_TX_ID_DELAY; +#endif + +#ifdef CONFIG_FIFO_DEPTH + dp83867->fifo_depth = CONFIG_FIFO_DEPTH; +#else + dp83867->fifo_depth = DEFAULT_FIFO_DEPTH; +#endif + return 0; +} static int dp83867_config(struct phy_device *phydev) { + struct dp83867_private *dp83867; unsigned int val, delay; int ret; + if (!phydev->priv) { + dp83867 = kzalloc(sizeof(*dp83867), GFP_KERNEL); + if (!dp83867) + return -ENOMEM; + + phydev->priv = dp83867; + ret = dp83867_data_init(phydev); + if (ret) + goto dp83867_write_error; + } else { + dp83867 = (struct dp83867_private *)phydev->priv; + } + /* Restart the PHY. */ val = phy_read(phydev, MDIO_DEVAD_NONE, DP83867_CTRL); phy_write(phydev, MDIO_DEVAD_NONE, DP83867_CTRL, @@ -152,9 +203,9 @@ static int dp83867_config(struct phy_device *phydev) if (phy_interface_is_rgmii(phydev)) { ret = phy_write(phydev, MDIO_DEVAD_NONE, MII_DP83867_PHYCTRL, (DP83867_MDI_CROSSOVER_AUTO << DP83867_MDI_CROSSOVER) | - (FIFO_DEPTH << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); if (ret) - return ret; + goto dp83867_write_error; } if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) && @@ -175,8 +226,8 @@ static int dp83867_config(struct phy_device *phydev) phy_write_mmd_indirect(phydev, DP83867_RGMIICTL, DP83867_DEVADDR, phydev->addr, val); - delay = (RX_ID_DELAY | - (TX_ID_DELAY << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); + delay = (dp83867->rx_id_delay | + (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT)); phy_write_mmd_indirect(phydev, DP83867_RGMIIDCTL, DP83867_DEVADDR, phydev->addr, delay); @@ -184,6 +235,10 @@ static int dp83867_config(struct phy_device *phydev) genphy_config_aneg(phydev); return 0; + +dp83867_write_error: + free(dp83867); + return ret; } static struct phy_driver DP83867_driver = { diff --git a/include/dt-bindings/net/ti-dp83867.h b/include/dt-bindings/net/ti-dp83867.h new file mode 100644 index 0000000..5c592fb --- /dev/null +++ b/include/dt-bindings/net/ti-dp83867.h @@ -0,0 +1,35 @@ +/* + * TI DP83867 PHY drivers + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#ifndef _DT_BINDINGS_TI_DP83867_H +#define _DT_BINDINGS_TI_DP83867_H + +/* PHY CTRL bits */ +#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00 +#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01 +#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02 +#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03 + +/* RGMIIDCTL internal delay for rx and tx */ +#define DP83867_RGMIIDCTL_250_PS 0x0 +#define DP83867_RGMIIDCTL_500_PS 0x1 +#define DP83867_RGMIIDCTL_750_PS 0x2 +#define DP83867_RGMIIDCTL_1_NS 0x3 +#define DP83867_RGMIIDCTL_1_25_NS 0x4 +#define DP83867_RGMIIDCTL_1_50_NS 0x5 +#define DP83867_RGMIIDCTL_1_75_NS 0x6 +#define DP83867_RGMIIDCTL_2_00_NS 0x7 +#define DP83867_RGMIIDCTL_2_25_NS 0x8 +#define DP83867_RGMIIDCTL_2_50_NS 0x9 +#define DP83867_RGMIIDCTL_2_75_NS 0xa +#define DP83867_RGMIIDCTL_3_00_NS 0xb +#define DP83867_RGMIIDCTL_3_25_NS 0xc +#define DP83867_RGMIIDCTL_3_50_NS 0xd +#define DP83867_RGMIIDCTL_3_75_NS 0xe +#define DP83867_RGMIIDCTL_4_00_NS 0xf + +#endif