From patchwork Wed Jun 15 19:26:35 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andreas Dannenberg X-Patchwork-Id: 70125 Delivered-To: patch@linaro.org Received: by 10.140.106.246 with SMTP id e109csp16909qgf; Wed, 15 Jun 2016 12:27:59 -0700 (PDT) X-Received: by 10.194.178.166 with SMTP id cz6mr296217wjc.102.1466018879401; Wed, 15 Jun 2016 12:27:59 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id lz8si912791wjb.35.2016.06.15.12.27.59; Wed, 15 Jun 2016 12:27:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D6B61A7727; Wed, 15 Jun 2016 21:27:36 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qs-o4NnG2ccn; Wed, 15 Jun 2016 21:27:36 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E7F27A7729; Wed, 15 Jun 2016 21:27:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7016DA754E for ; Wed, 15 Jun 2016 21:26:58 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aGupGcJzQ44p for ; Wed, 15 Jun 2016 21:26:58 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from devils.ext.ti.com (devils.ext.ti.com [198.47.26.153]) by theia.denx.de (Postfix) with ESMTPS id BDD33A769B for ; Wed, 15 Jun 2016 21:26:53 +0200 (CEST) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by devils.ext.ti.com (8.13.7/8.13.7) with ESMTP id u5FJQNrn022209; Wed, 15 Jun 2016 14:26:23 -0500 Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id u5FJQoVR019405; Wed, 15 Jun 2016 14:26:50 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Wed, 15 Jun 2016 14:26:49 -0500 Received: from borg.dal.design.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id u5FJQnBV003642; Wed, 15 Jun 2016 14:26:50 -0500 From: Andreas Dannenberg To: , Tom Rini , Simon Glass Date: Wed, 15 Jun 2016 14:26:35 -0500 Message-ID: <1466018801-18044-4-git-send-email-dannenberg@ti.com> X-Mailer: git-send-email 2.7.2 In-Reply-To: <1466018801-18044-1-git-send-email-dannenberg@ti.com> References: <1466018801-18044-1-git-send-email-dannenberg@ti.com> MIME-Version: 1.0 Cc: Madan Srinivas , Daniel Allred Subject: [U-Boot] [RFC 3/9] arm: omap-common: add secure smc entry X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Daniel Allred Adds an interface for calling secure ROM APIs across a range of OMAP and OMAP compatible devices. Signed-off-by: Daniel Allred Signed-off-by: Andreas Dannenberg --- arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 47 ++++++++++++++++++++++---- arch/arm/include/asm/omap_common.h | 2 ++ 2 files changed, 42 insertions(+), 7 deletions(-) -- 2.6.4 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S index 5283135..2a710ce 100644 --- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S +++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S @@ -16,6 +16,8 @@ #include #include +.arch_extension sec + #ifdef CONFIG_SPL ENTRY(save_boot_params) @@ -26,14 +28,45 @@ ENDPROC(save_boot_params) #endif ENTRY(omap_smc1) - PUSH {r4-r12, lr} @ save registers - ROM code may pollute + push {r4-r12, lr} @ save registers - ROM code may pollute @ our registers - MOV r12, r0 @ Service - MOV r0, r1 @ Argument - DSB - DMB - .word 0xe1600070 @ SMC #0 - hand assembled for GCC versions + mov r12, r0 @ Service + mov r0, r1 @ Argument + dsb + dmb + smc 0 @ SMC #0 to enter monitor mode @ call ROM Code API for the service requested - POP {r4-r12, pc} + pop {r4-r12, pc} ENDPROC(omap_smc1) + +ENTRY(omap_smc_sec) + push {r4-r12, lr} @ save registers - ROM code may pollute + + mov r6, #0xFF @ Indicate new Task call + + mov r12, #0x00 @ Secure Service ID in R12 + + dsb + dmb + + smc 0 @ SMC #0 to enter monitor mode + b omap_smc_sec_end /* exit at end of the service execution */ + nop + + /* In case of IRQ happening in Secure, then ARM will branch here. + * At that moment, IRQ will be pending and ARM will jump to Non Secure + * IRQ handler + */ + mov r12, #0xFE + + dsb + dmb + + smc 0 @ SMC #0 to enter monitor mode + +omap_smc_sec_end: + pop {r4-r12, lr} + bx lr + +ENDPROC(omap_smc_sec) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 07f3848..5943e6f 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -627,6 +627,8 @@ void recalibrate_iodelay(void); void omap_smc1(u32 service, u32 val); +u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params); + void enable_edma3_clocks(void); void disable_edma3_clocks(void);