From patchwork Thu Oct 27 14:47:08 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Masahiro Yamada X-Patchwork-Id: 79698 Delivered-To: patch@linaro.org Received: by 10.80.142.83 with SMTP id 19csp686431edx; Thu, 27 Oct 2016 07:49:58 -0700 (PDT) X-Received: by 10.28.211.130 with SMTP id k124mr8701608wmg.122.1477579798902; Thu, 27 Oct 2016 07:49:58 -0700 (PDT) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id l5si3658576wml.40.2016.10.27.07.49.58; Thu, 27 Oct 2016 07:49:58 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@nifty.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1FAA4A75FA; Thu, 27 Oct 2016 16:48:41 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id LXrwMksJ1a0m; Thu, 27 Oct 2016 16:48:41 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 9B9E8A75BA; Thu, 27 Oct 2016 16:48:15 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E231EA7576 for ; Thu, 27 Oct 2016 16:47:50 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pBnP_1sOBFmM for ; Thu, 27 Oct 2016 16:47:50 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from conuserg-07.nifty.com (conuserg-07.nifty.com [210.131.2.74]) by theia.denx.de (Postfix) with ESMTPS id 9A4AAB381C for ; Thu, 27 Oct 2016 16:47:49 +0200 (CEST) Received: from grover.sesame (FL1-111-169-71-157.osk.mesh.ad.jp [111.169.71.157]) (authenticated) by conuserg-07.nifty.com with ESMTP id u9RElDVR017011; Thu, 27 Oct 2016 23:47:26 +0900 DKIM-Filter: OpenDKIM Filter v2.10.3 conuserg-07.nifty.com u9RElDVR017011 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nifty.com; s=dec2015msa; t=1477579647; bh=Dod7UYJZ1OaOLiZ9nqYc5xWx4exNpUMYKTxO99eUetU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=bNznylPJsBYcQ8lOT0yMwPo0dRd5cu+nN4SaJGq71xBPxHcmcpOG6aOFfqesUHorM +8q6suTLW2h4+9mnxEi5rEp3TvfSWLyeydXzGAoWILeKDIbQ4Kx0S2B/QVe2PAH8FS QsX2iiKK7/AoHWZ3cxAH11Degv1lanJns2TsCnZmVzpYAysQ4NraGPjz4vcs9hac/r o2CNFTC5QEVHveR8/xqx3ACN9gon3M7moFZn7v6d7K2VoiDwCOHppJFCLaXEMqShTy 6EEif8zS9c+2AZrBnOselltRmiEpqCXYfmIQ/wjBMHYZ9x595mPID9RKk4BUhRapKT iaGT0Mv2DJT4Q== X-Nifty-SrcIP: [111.169.71.157] From: Masahiro Yamada To: u-boot@lists.denx.de Date: Thu, 27 Oct 2016 23:47:08 +0900 Message-Id: <1477579630-9692-10-git-send-email-yamada.masahiro@socionext.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477579630-9692-1-git-send-email-yamada.masahiro@socionext.com> References: <1477579630-9692-1-git-send-email-yamada.masahiro@socionext.com> Cc: Albert Aribaud Subject: [U-Boot] [PATCH 09/11] ARM: uniphier: refactor DDR PHY parameter dump command X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Do not hard-code the number of DX blocks because it is a different value for LD11 SoC. Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it is the last user. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram/cmd_ddrphy.c | 88 ++++++++++++++------------- arch/arm/mach-uniphier/dram/ddrphy-init.h | 3 - arch/arm/mach-uniphier/dram/ddrphy-training.c | 3 + 3 files changed, 50 insertions(+), 44 deletions(-) -- 1.9.1 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot diff --git a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c index 3dae129..c868eb0 100644 --- a/arch/arm/mach-uniphier/dram/cmd_ddrphy.c +++ b/arch/arm/mach-uniphier/dram/cmd_ddrphy.c @@ -11,7 +11,6 @@ #include #include "../soc-info.h" -#include "ddrphy-init.h" #include "ddrphy-regs.h" /* Select either decimal or hexadecimal */ @@ -23,22 +22,29 @@ /* field separator */ #define FS " " -static unsigned long uniphier_ld4_base[] = { - 0x5bc01000, - 0x5be01000, - 0 /* sentinel */ +struct phy_param { + resource_size_t base; + unsigned int nr_dx; }; -static unsigned long uniphier_pro4_base[] = { - 0x5bc01000, - 0x5be01000, - 0 /* sentinel */ +static const struct phy_param uniphier_ld4_phy_param[] = { + { .base = 0x5bc01000, .nr_dx = 2, }, + { .base = 0x5be01000, .nr_dx = 2, }, + { /* sentinel */ } }; -static unsigned long uniphier_sld8_base[] = { - 0x5bc01000, - 0x5be01000, - 0 /* sentinel */ +static const struct phy_param uniphier_pro4_phy_param[] = { + { .base = 0x5bc01000, .nr_dx = 2, }, + { .base = 0x5bc02000, .nr_dx = 2, }, + { .base = 0x5be01000, .nr_dx = 2, }, + { .base = 0x5be02000, .nr_dx = 2, }, + { /* sentinel */ } +}; + +static const struct phy_param uniphier_sld8_phy_param[] = { + { .base = 0x5bc01000, .nr_dx = 2, }, + { .base = 0x5be01000, .nr_dx = 2, }, + { /* sentinel */ } }; static void print_bdl(void __iomem *reg, int n) @@ -50,17 +56,17 @@ static void print_bdl(void __iomem *reg, int n) printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f); } -static void dump_loop(unsigned long *base, +static void dump_loop(const struct phy_param *phy_param, void (*callback)(void __iomem *)) { void __iomem *phy_base, *dx_base; int p, dx; - for (p = 0; *base; base++, p++) { - phy_base = ioremap(*base, SZ_4K); + for (p = 0; phy_param->base; phy_param++, p++) { + phy_base = ioremap(phy_param->base, SZ_4K); dx_base = phy_base + PHY_DX_BASE; - for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + for (dx = 0; dx < phy_param->nr_dx; dx++) { printf("PHY%dDX%d:", p, dx); (*callback)(dx_base); dx_base += PHY_DX_STRIDE; @@ -80,12 +86,12 @@ static void __wbdl_dump(void __iomem *dx_base) readl(dx_base + PHY_DX_LCDLR1) & 0xff); } -static void wbdl_dump(unsigned long *base) +static void wbdl_dump(const struct phy_param *phy_param) { printf("\n--- Write Bit Delay Line ---\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); - dump_loop(base, &__wbdl_dump); + dump_loop(phy_param, &__wbdl_dump); } static void __rbdl_dump(void __iomem *dx_base) @@ -97,12 +103,12 @@ static void __rbdl_dump(void __iomem *dx_base) (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff); } -static void rbdl_dump(unsigned long *base) +static void rbdl_dump(const struct phy_param *phy_param) { printf("\n--- Read Bit Delay Line ---\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n"); - dump_loop(base, &__rbdl_dump); + dump_loop(phy_param, &__rbdl_dump); } static void __wld_dump(void __iomem *dx_base) @@ -120,12 +126,12 @@ static void __wld_dump(void __iomem *dx_base) } } -static void wld_dump(unsigned long *base) +static void wld_dump(const struct phy_param *phy_param) { printf("\n--- Write Leveling Delay ---\n"); printf(" Rank0 Rank1 Rank2 Rank3\n"); - dump_loop(base, &__wld_dump); + dump_loop(phy_param, &__wld_dump); } static void __dqsgd_dump(void __iomem *dx_base) @@ -142,12 +148,12 @@ static void __dqsgd_dump(void __iomem *dx_base) } } -static void dqsgd_dump(unsigned long *base) +static void dqsgd_dump(const struct phy_param *phy_param) { printf("\n--- DQS Gating Delay ---\n"); printf(" Rank0 Rank1 Rank2 Rank3\n"); - dump_loop(base, &__dqsgd_dump); + dump_loop(phy_param, &__dqsgd_dump); } static void __mdl_dump(void __iomem *dx_base) @@ -158,12 +164,12 @@ static void __mdl_dump(void __iomem *dx_base) printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); } -static void mdl_dump(unsigned long *base) +static void mdl_dump(const struct phy_param *phy_param) { printf("\n--- Master Delay Line ---\n"); printf(" IPRD TPRD MDLD\n"); - dump_loop(base, &__mdl_dump); + dump_loop(phy_param, &__mdl_dump); } #define REG_DUMP(x) \ @@ -178,15 +184,15 @@ static void mdl_dump(unsigned long *base) printf("%3d: DX%d%-7s: %p : %08x\n", \ ofst >> PHY_REG_SHIFT, (dx), #x, reg, readl(reg)); } -static void reg_dump(unsigned long *base) +static void reg_dump(const struct phy_param *phy_param) { void __iomem *phy_base; int p, dx; printf("\n--- DDR PHY registers ---\n"); - for (p = 0; *base; base++, p++) { - phy_base = ioremap(*base, SZ_4K); + for (p = 0; phy_param->base; phy_param++, p++) { + phy_base = ioremap(phy_param->base, SZ_4K); printf("== PHY%d (base: %p) ==\n", p, phy_base); printf(" No: Name : Address : Data\n"); @@ -216,7 +222,7 @@ static void reg_dump(unsigned long *base) REG_DUMP(MR2); REG_DUMP(MR3); - for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { + for (dx = 0; dx < phy_param->nr_dx; dx++) { DX_REG_DUMP(dx, GCR); DX_REG_DUMP(dx, GTR); } @@ -228,17 +234,17 @@ static void reg_dump(unsigned long *base) static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char *cmd = argv[1]; - unsigned long *base; + const struct phy_param *phy_param; switch (uniphier_get_soc_type()) { case SOC_UNIPHIER_LD4: - base = uniphier_ld4_base; + phy_param = uniphier_ld4_phy_param; break; case SOC_UNIPHIER_PRO4: - base = uniphier_pro4_base; + phy_param = uniphier_pro4_phy_param; break; case SOC_UNIPHIER_SLD8: - base = uniphier_sld8_base; + phy_param = uniphier_sld8_phy_param; break; default: printf("unsupported SoC\n"); @@ -249,22 +255,22 @@ static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) cmd = "all"; if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all")) - wbdl_dump(base); + wbdl_dump(phy_param); if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all")) - rbdl_dump(base); + rbdl_dump(phy_param); if (!strcmp(cmd, "wld") || !strcmp(cmd, "all")) - wld_dump(base); + wld_dump(phy_param); if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all")) - dqsgd_dump(base); + dqsgd_dump(phy_param); if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all")) - mdl_dump(base); + mdl_dump(phy_param); if (!strcmp(cmd, "reg") || !strcmp(cmd, "all")) - reg_dump(base); + reg_dump(phy_param); return CMD_RET_SUCCESS; } diff --git a/arch/arm/mach-uniphier/dram/ddrphy-init.h b/arch/arm/mach-uniphier/dram/ddrphy-init.h index 3fc610b..4216745 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-init.h +++ b/arch/arm/mach-uniphier/dram/ddrphy-init.h @@ -10,9 +10,6 @@ #include #include -/* for LD4, Pro4, sLD8 */ -#define NR_DATX8_PER_DDRPHY 2 - int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus); void ddrphy_prepare_training(void __iomem *phy_base, int rank); int ddrphy_training(void __iomem *phy_base); diff --git a/arch/arm/mach-uniphier/dram/ddrphy-training.c b/arch/arm/mach-uniphier/dram/ddrphy-training.c index 2ea5c77..b161dbf 100644 --- a/arch/arm/mach-uniphier/dram/ddrphy-training.c +++ b/arch/arm/mach-uniphier/dram/ddrphy-training.c @@ -11,6 +11,9 @@ #include "ddrphy-init.h" #include "ddrphy-regs.h" +/* for LD4, Pro4, sLD8 */ +#define NR_DATX8_PER_DDRPHY 2 + void ddrphy_prepare_training(void __iomem *phy_base, int rank) { void __iomem *dx_base = phy_base + PHY_DX_BASE;