From patchwork Tue Jan 10 11:28:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sjoerd Simons X-Patchwork-Id: 90676 Delivered-To: patch@linaro.org Received: by 10.140.20.99 with SMTP id 90csp570616qgi; Tue, 10 Jan 2017 03:35:50 -0800 (PST) X-Received: by 10.223.138.220 with SMTP id z28mr1610628wrz.26.1484048150047; Tue, 10 Jan 2017 03:35:50 -0800 (PST) Return-Path: Received: from theia.denx.de (theia.denx.de. [85.214.87.163]) by mx.google.com with ESMTP id xs6si1398124wjc.244.2017.01.10.03.35.49; Tue, 10 Jan 2017 03:35:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) client-ip=85.214.87.163; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 85.214.87.163 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=collabora.co.uk Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id CDE1BB38D4; Tue, 10 Jan 2017 12:35:47 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Os4XvUINwFY9; Tue, 10 Jan 2017 12:35:47 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4366BB38B0; Tue, 10 Jan 2017 12:35:47 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3E572B38B0 for ; Tue, 10 Jan 2017 12:35:43 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id xUvb1g-za5yR for ; Tue, 10 Jan 2017 12:35:43 +0100 (CET) X-Greylist: delayed 400 seconds by postgrey-1.34 at theia; Tue, 10 Jan 2017 12:35:40 CET X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [46.235.227.227]) by theia.denx.de (Postfix) with ESMTPS id 0AB3EB384C for ; Tue, 10 Jan 2017 12:35:40 +0100 (CET) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: sjoerd) with ESMTPSA id D3CA22696AB Received: by dawn.luon.net (Postfix, from userid 1000) id C85F4186219E; Tue, 10 Jan 2017 12:28:57 +0100 (CET) From: Sjoerd Simons To: u-boot@lists.denx.de Date: Tue, 10 Jan 2017 12:28:57 +0100 Message-Id: <20170110112857.30074-1-sjoerd.simons@collabora.co.uk> X-Mailer: git-send-email 2.11.0 Cc: Javier Martinez Canillas Subject: [U-Boot] [PATCH] exynos5: Don't potentially undervoltage the CPU X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For snow when chainloading u-boot the CPU seems to be running at full speed. The lower CPU voltage seems to be ok for u-boot, but when booting linux (bringing up all cores) I'm seeing random crashes. Bump the voltage up to a level that's safe for all cpu frequencies. Signed-off-by: Sjoerd Simons --- board/samsung/common/exynos5-dt.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) -- 2.11.0 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot Reviewed-by: Javier Martinez Canillas diff --git a/board/samsung/common/exynos5-dt.c b/board/samsung/common/exynos5-dt.c index 2e3b16df45..aec1f396b0 100644 --- a/board/samsung/common/exynos5-dt.c +++ b/board/samsung/common/exynos5-dt.c @@ -123,13 +123,7 @@ int exynos_power_init(void) if (ret) return ret; - /* - * This would normally be 1.3V, but since we are running slowly 1.1V - * is enough. For spring it helps reduce CPU temperature and avoid - * hangs with the case open. 1.1V is minimum voltage borderline for - * chained bootloaders. - */ - ret = exynos_set_regulator("vdd_arm", 1100000); + ret = exynos_set_regulator("vdd_arm", 1300000); if (ret) return ret; ret = exynos_set_regulator("vdd_int", 1012500);