From patchwork Sat Aug 5 02:42:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 109475 Delivered-To: patch@linaro.org Received: by 10.140.101.6 with SMTP id t6csp97231qge; Fri, 4 Aug 2017 19:43:08 -0700 (PDT) X-Received: by 10.80.149.145 with SMTP id w17mr4395708eda.82.1501900987973; Fri, 04 Aug 2017 19:43:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1501900987; cv=none; d=google.com; s=arc-20160816; b=f0ect/UJzMcObDugK+Qti2r1uOtP8XPmMnBjBF5RBqaKnDG9ifSABbEcU/0RqouKXq CremhmNrjW+AJzcxryyLfpJR1/gFC7LMpgerkpTYmjsISxfgxfZ98RoGPihPFZl4OkSS tTZ2zd8UiFBLQyIB/WbTm0D/mP3nb2BPKl70fx5y+iahOjb/cHinN3aGWIsxrq/YXgNh 4OkIFxCzTnPtZ+26TvlFjpvev/+Pr7ZlseS/+Saef9W0diISdrcrVzWinLwUvjFdinyQ ZXF5SQr+wpCdpR58xQAAKSiBjyWm32IWv1bkfWfZxoZC6LMTejSnBB2AVeA2T8Oa/zTM aX1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:list-subscribe:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence:subject :cc:mime-version:references:in-reply-to:message-id:date:to:from :dkim-signature:arc-authentication-results; bh=yMrQJpC9W9X9MUVAX3xQJmcShY0SG6rI43UgoSc2/A4=; b=W3+pOm1xiPNK/DJBw+/hevIT5HhJ30eE4gq9Da7xN2quH7Snw8y+bqnWkIWf1+wtEr lZz+Fl8X0hgRGNePVLSYrWc+sZ4LbnZAUqLV4rd0tEDTahxLqtBIiDXpJ5VxDQzlqnYY BTYJYV2A4v5Yx5GcjT3Gm2VRmJbW3p7VQgL/F0LUL9/Ak3yzE8hyyPy6a2GOVi1ER3kW o0LtW5Bf2d1DPk8LZnxqqCgKtjzEI3ZsCKIkeAETQhG+mGQYuHmXmzmJSQpMkIZAOPpt A5S7WTtcHLao8qnK7C0UWon8b5pDt34458icDSSoxhvekgBn9OnRjBFt0KQsAWTuhgF0 3siQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.b=LLmqdMpQ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from lists.denx.de (dione.denx.de. [81.169.180.215]) by mx.google.com with ESMTP id q13si6125498edk.226.2017.08.04.19.43.07; Fri, 04 Aug 2017 19:43:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) client-ip=81.169.180.215; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@ti.com header.b=LLmqdMpQ; spf=pass (google.com: best guess record for domain of u-boot-bounces@lists.denx.de designates 81.169.180.215 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: by lists.denx.de (Postfix, from userid 105) id 7D310C21F97; Sat, 5 Aug 2017 02:42:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_NONE, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9B38DC21F51; Sat, 5 Aug 2017 02:42:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8CC16C21DE1; Sat, 5 Aug 2017 02:42:13 +0000 (UTC) Received: from lelnx193.ext.ti.com (lelnx193.ext.ti.com [198.47.27.77]) by lists.denx.de (Postfix) with ESMTPS id C8F1CC21C2B for ; Sat, 5 Aug 2017 02:42:12 +0000 (UTC) Received: from dlelxv90.itg.ti.com ([172.17.2.17]) by lelnx193.ext.ti.com (8.15.1/8.15.1) with ESMTP id v752gAHc008245; Fri, 4 Aug 2017 21:42:10 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ti.com; s=ti-com-17Q1; t=1501900930; bh=2VaT5c/1xd6rWlMLTX6hqfN0U9ob7B8jFZmSxlsnWb0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=LLmqdMpQCoalz5WYvfk/MDSWky6Z6oRz4WLX07Mrq9HS/ddXp4gg72CkPEmaMgutk Mci5CgR7aIBI9AN2luG+W2Be3gApR2u7v1WpmEcinTvNSWjDaWt4MbJf48w0i62oIs P0YAlktR6PrjBK33K5canhQPa2CCvTPf1j8UaBgc= Received: from DLEE70.ent.ti.com (dlee70.ent.ti.com [157.170.170.113]) by dlelxv90.itg.ti.com (8.14.3/8.13.8) with ESMTP id v752gApv016217; Fri, 4 Aug 2017 21:42:10 -0500 Received: from dflp32.itg.ti.com (10.64.6.15) by DLEE70.ent.ti.com (157.170.170.113) with Microsoft SMTP Server id 14.3.294.0; Fri, 4 Aug 2017 21:42:10 -0500 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp32.itg.ti.com (8.14.3/8.13.8) with ESMTP id v752gAdW028556; Fri, 4 Aug 2017 21:42:10 -0500 From: Nishanth Menon To: Tom Rini , Lokesh Vutla Date: Fri, 4 Aug 2017 21:42:09 -0500 Message-ID: <20170805024209.3703-3-nm@ti.com> X-Mailer: git-send-email 2.12.2 In-Reply-To: <20170805024209.3703-1-nm@ti.com> References: <20170805024209.3703-1-nm@ti.com> MIME-Version: 1.0 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 2/2] ARM: OMAP5: Enable support for AVS0 for OMAP5 production devices X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" OMAP5432 did go into production with AVS class0 registers which were mutually exclusive from AVS Class 1.5 registers. Most OMAP5-uEVM boards use the pre-production Class1.5 which has production efuse registers set to 0. However on production devices, these are set to valid data. scale_vcore logic is already smart enough to detect this and use the "Nominal voltage" on devices that do not have efuse registers populated. On a test production device populated as follows: MPU OPP_NOM: => md.l 0x04A0021C4 1 4a0021c4: 03a003e9 .... (0x3e9 = 1.01v) vs nom voltage of 1.06v MPU OPP_HIGH: => md.l 0x04A0021C8 1 4a0021c8: 03400485 ..@. MM OPP_NOM: => md.l 0x04A0021A4 1 4a0021a4: 038003d4 .... (0x3d4 = 980mV) vs nom voltage of 1.025v MM OPP_OD: => md.l 0x04A0021A8 1 4a0021a8: 03600403 ..`. CORE OPP_NOM: => md.l 0x04A0021D8 1 4a0021d8: 000003cf .... (0x3cf = 975mV) vs nom voltage of 1.040v Since the efuse values are'nt currently used, we do not regress on existing pre-production samples (they continue to use nominal voltage). But on boards that do have production samples populated, we can leverage the optimal voltages necessary for proper operation. Tested on: a) 720-2644-001 OMAP5UEVM with production sample. b) 750-2628-222(A) UEVM5432G-02 with pre-production sample. Data based on OMAP5432 Technical reference Manual SWPU282AF (May 2012-Revised Aug 2016) NOTE: All collaterals on OMAP5432 silicon itself seems to have been removed from ti.com, though EVM details are still available: http://www.ti.com/tool/OMAP5432-EVM Signed-off-by: Nishanth Menon Reviewed-by: Lokesh Vutla --- arch/arm/include/asm/arch-omap5/clock.h | 16 ++++++++++++++++ arch/arm/include/asm/arch-omap5/omap.h | 4 ++-- arch/arm/mach-omap2/omap5/abb.c | 4 ++-- arch/arm/mach-omap2/omap5/hw_data.c | 9 +++++++++ 4 files changed, 29 insertions(+), 4 deletions(-) diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h index dd05e8ba8317..dbe340d23e4f 100644 --- a/arch/arm/include/asm/arch-omap5/clock.h +++ b/arch/arm/include/asm/arch-omap5/clock.h @@ -236,6 +236,22 @@ #define VDD_MPU_ES2_HIGH 1250 #define VDD_MM_ES2_OD 1120 +/* Efuse register offsets for OMAP5 platform */ +#define OMAP5_ES2_EFUSE_BASE 0x4A002000 +#define OMAP5_ES2_PROD_REGBITS 16 + +/* CONTROL_STD_FUSE_OPP_VDD_CORE_3 */ +#define OMAP5_ES2_PROD_CORE_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1D8) + +/* CONTROL_STD_FUSE_OPP_VDD_MM_4 */ +#define OMAP5_ES2_PROD_MM_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A4) +/* CONTROL_STD_FUSE_OPP_VDD_MM_5 */ +#define OMAP5_ES2_PROD_MM_OPOD_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1A8) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_6 */ +#define OMAP5_ES2_PROD_MPU_OPNO_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C4) +/* CONTROL_STD_FUSE_OPP_VDD_MPU_7 */ +#define OMAP5_ES2_PROD_MPU_OPHI_VMIN (OMAP5_ES2_EFUSE_BASE + 0x1C8) + /* DRA74x/75x/72x voltage settings in mv for OPP_NOM per DM */ #define VDD_MPU_DRA7_NOM 1150 #define VDD_CORE_DRA7_NOM 1150 diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 2f005dd3ad92..b047f0d65081 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -224,8 +224,8 @@ struct s32ktimer { #define OMAP_ABB_GPU_TXDONE_MASK (0x1 << 28) /* ABB efuse masks */ -#define OMAP5_ABB_FUSE_VSET_MASK (0x1F << 24) -#define OMAP5_ABB_FUSE_ENABLE_MASK (0x1 << 29) +#define OMAP5_PROD_ABB_FUSE_VSET_MASK (0x1F << 20) +#define OMAP5_PROD_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define DRA7_ABB_FUSE_VSET_MASK (0x1F << 20) #define DRA7_ABB_FUSE_ENABLE_MASK (0x1 << 25) #define OMAP5_ABB_LDOVBBMPU_MUX_CTRL_MASK (0x1 << 10) diff --git a/arch/arm/mach-omap2/omap5/abb.c b/arch/arm/mach-omap2/omap5/abb.c index 3bf88979e5d6..1882c49e7df6 100644 --- a/arch/arm/mach-omap2/omap5/abb.c +++ b/arch/arm/mach-omap2/omap5/abb.c @@ -28,8 +28,8 @@ s8 abb_setup_ldovbb(u32 fuse, u32 ldovbb) { u32 vset; - u32 fuse_enable_mask = OMAP5_ABB_FUSE_ENABLE_MASK; - u32 fuse_vset_mask = OMAP5_ABB_FUSE_VSET_MASK; + u32 fuse_enable_mask = OMAP5_PROD_ABB_FUSE_ENABLE_MASK; + u32 fuse_vset_mask = OMAP5_PROD_ABB_FUSE_VSET_MASK; if (!is_omap54xx()) { /* DRA7 */ diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c index a8a6b8a869e5..4ad6b530d29c 100644 --- a/arch/arm/mach-omap2/omap5/hw_data.c +++ b/arch/arm/mach-omap2/omap5/hw_data.c @@ -329,6 +329,15 @@ struct vcores_data omap5430_volts_es2 = { .mm.addr = SMPS_REG_ADDR_45_IVA, .mm.pmic = &palmas, .mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK, + + .mpu.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MPU_OPNO_VMIN, + .mpu.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, + + .core.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_CORE_OPNO_VMIN, + .core.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, + + .mm.efuse.reg[OPP_NOM] = OMAP5_ES2_PROD_MM_OPNO_VMIN, + .mm.efuse.reg_bits = OMAP5_ES2_PROD_REGBITS, }; /*