diff mbox series

[v1,7/8] riscv: Add device tree bindings for SPI

Message ID 20200305191925.959494-8-seanga2@gmail.com
State New
Headers show
Series riscv: Add SPI support for Kendryte K210 | expand

Commit Message

Sean Anderson March 5, 2020, 7:19 p.m. UTC 
This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix
Bit.

Signed-off-by: Sean Anderson <seanga2 at gmail.com>
---

 arch/riscv/dts/k210-maix-bit.dts | 90 ++++++++++++++++++++++++++++++++
 arch/riscv/dts/k210.dtsi         | 12 +++++
 2 files changed, 102 insertions(+)

Comments

Marek Vasut March 22, 2020, 1:55 a.m. UTC | #1 
On 3/5/20 8:19 PM, Sean Anderson wrote:
> This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix
> Bit.

The mail subject should say this is for specific SoC.
[...]

> +&wdt0 {
> +	status = "okay";
>  };

This shouldn't be here I guess ?

You should split this into the .dtsi addition for SoC and board specific
patch.
Sean Anderson March 22, 2020, 2:39 a.m. UTC | #2 
On 3/21/20 9:55 PM, Marek Vasut wrote:
> On 3/5/20 8:19 PM, Sean Anderson wrote:
>> This patch adds bindings for the MMC slot and SPI flash on the Sipeed Maix
>> Bit.
> 
> The mail subject should say this is for specific SoC
Oh, whoops. This will be fixed in the next revision.

> [...]
> 
>> +&wdt0 {
>> +	status = "okay";
>>  };
> 
> This shouldn't be here I guess ?

Yeah, this was meant to be added in a separate series for the wdt.

> 
> You should split this into the .dtsi addition for SoC and board specific
> patch.

Ok.

--Sean
diff mbox series

Patch

diff --git a/arch/riscv/dts/k210-maix-bit.dts b/arch/riscv/dts/k210-maix-bit.dts
index c0ec572552..cb4dba5e13 100644
--- a/arch/riscv/dts/k210-maix-bit.dts
+++ b/arch/riscv/dts/k210-maix-bit.dts
@@ -235,9 +235,99 @@ 
 			pins = "IO_47";
 		};
 	};
+
+	fpioa_spi0: spi0 {
+		cs0 {
+			function = "GPIOHS28";
+			pins = "IO_36";
+		};
+		rst {
+			function = "GPIOHS29";
+			pins = "IO_37";
+		};
+		dc {
+			function = "GPIOHS30";
+			pins = "IO_38";
+		};
+		wr {
+			function = "SPI0_SCK";
+			pins = "IO_39";
+		};
+	};
+
+	fpioa_spi1: spi1 {
+		miso {
+			function = "SPI1_D1";
+			pins = "IO_26";
+		};
+		clk {
+			function = "SPI1_SCLK";
+			pins = "IO_27";
+		};
+		mosi {
+			function = "SPI1_D0";
+			pins = "IO_28";
+		};
+		cs0 {
+			function = "GPIOHS31";
+			pins = "IO_29";
+		};
+	};
+};
+
+&wdt0 {
+	status = "okay";
 };
 
 &dvp0 {
 	pinctrl-0 = <&fpioa_dvp>;
 	pinctrl-names = "default";
 };
+
+&spi0 {
+	pinctrl-0 = <&fpioa_spi0>;
+	pinctrl-names = "default";
+	num-cs = <1>;
+	cs-gpios = <&gpio0 28 0>;
+
+	panel at 0 {
+		compatible = "sitronix,st8898v";
+		reg = <0>;
+		reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+		spi-max-frequency = <15000000>;
+		status = "disabled";
+	};
+};
+
+&spi1 {
+	pinctrl-0 = <&fpioa_spi1>;
+	pinctrl-names = "default";
+	num-cs = <1>;
+	cs-gpios = <&gpio0 31 0>;
+	status = "okay";
+
+	slot at 0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <25000000>;
+		voltage-ranges = <3300 3300>;
+		broken-cd;
+		disable-wp;
+	};
+};
+
+&spi3 {
+	status = "okay";
+
+	spi-flash at 0 {
+		compatible = "winbond,w25q128fw", "jedec,spi-nor";
+		reg = <0>;
+		/*
+		 * Datasheet says it should work at 100 MHz with fast read, but
+		 * after testing it doesn't probe at that frequency
+		 */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		broken-flash-reset;
+	};
+};
diff --git a/arch/riscv/dts/k210.dtsi b/arch/riscv/dts/k210.dtsi
index 0192ce5eae..a74620281c 100644
--- a/arch/riscv/dts/k210.dtsi
+++ b/arch/riscv/dts/k210.dtsi
@@ -592,6 +592,10 @@ 
 				spi-max-frequency = <25000000>;
 				num-cs = <4>;
 				reg-io-width = <4>;
+				snps,dfs-offset = <16>;
+				snps,frf-offset = <21>;
+				snps,tmod-offset = <8>;
+				snps,mode-offset = <6>;
 				status = "disabled";
 			};
 
@@ -608,6 +612,10 @@ 
 				spi-max-frequency = <25000000>;
 				num-cs = <4>;
 				reg-io-width = <4>;
+				snps,dfs-offset = <16>;
+				snps,frf-offset = <21>;
+				snps,tmod-offset = <8>;
+				snps,mode-offset = <6>;
 				status = "disabled";
 			};
 
@@ -625,6 +633,10 @@ 
 				spi-max-frequency = <100000000>;
 				num-cs = <4>;
 				reg-io-width = <4>;
+				snps,dfs-offset = <0>;
+				snps,frf-offset = <22>;
+				snps,tmod-offset = <10>;
+				snps,mode-offset = <8>;
 				status = "disabled";
 			};
 		};