From patchwork Wed Apr 22 13:52:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peng Fan X-Patchwork-Id: 238309 List-Id: U-Boot discussion From: peng.fan at nxp.com (Peng Fan) Date: Wed, 22 Apr 2020 21:52:22 +0800 Subject: [PATCH 11/24] imx8mq: Enable eMMC HS400 and SD UHS mode on EVK In-Reply-To: <20200422135235.14756-1-peng.fan@nxp.com> References: <20200422135235.14756-1-peng.fan@nxp.com> Message-ID: <20200422135235.14756-11-peng.fan@nxp.com> From: Ye Li iMX8MQ EVK board has a eMMC5.0 chip and supports SD3.0, so enable the UHS and HS400 configs to enhance the eMMC/SD access. The change also needs to set usdhc clock to 400Mhz, and add the off-on-delay-us to SD reset pin, otherwise some SD cards will fail to select UHS mode in re-initialization. Signed-off-by: Ye Li Signed-off-by: Peng Fan --- arch/arm/mach-imx/imx8m/clock_imx8mq.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mq.c b/arch/arm/mach-imx/imx8m/clock_imx8mq.c index aad9cf13ef..76104e4f92 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mq.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mq.c @@ -428,15 +428,13 @@ void init_clk_usdhc(u32 index) case 0: clock_enable(CCGR_USDHC1, 0); clock_set_target_val(USDHC1_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + CLK_ROOT_SOURCE_SEL(1)); clock_enable(CCGR_USDHC1, 1); return; case 1: clock_enable(CCGR_USDHC2, 0); clock_set_target_val(USDHC2_CLK_ROOT, CLK_ROOT_ON | - CLK_ROOT_SOURCE_SEL(1) | - CLK_ROOT_POST_DIV(CLK_ROOT_POST_DIV2)); + CLK_ROOT_SOURCE_SEL(1)); clock_enable(CCGR_USDHC2, 1); return; default: