From patchwork Wed Apr 29 19:14:03 2020
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X-Patchwork-Submitter: Marek Vasut <marex@denx.de>
X-Patchwork-Id: 238911
List-Id: U-Boot discussion <u-boot.lists.denx.de>
From: marex at denx.de (Marek Vasut)
Date: Wed, 29 Apr 2020 21:14:03 +0200
Subject: [PATCH] net: dwc_eth_qos: Pad descriptors to cacheline size
Message-ID: <20200429191403.112487-1-marex@denx.de>

The DWMAC4 IP has the possibility to skip up to 7 64bit words after
the descriptor, use this to pad the descriptors to cacheline size.

Signed-off-by: Marek Vasut <marex at denx.de>
Cc: Joe Hershberger <joe.hershberger at ni.com>
Cc: Patrice Chotard <patrice.chotard at st.com>
Cc: Patrick Delaunay <patrick.delaunay at st.com>
Cc: Ramon Fried <rfried.dev at gmail.com>
Cc: Stephen Warren <swarren at nvidia.com>
---
 drivers/net/dwc_eth_qos.c | 28 ++++++++++++++++++----------
 1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
index 60dfd17a74..7fc91ed9a5 100644
--- a/drivers/net/dwc_eth_qos.c
+++ b/drivers/net/dwc_eth_qos.c
@@ -188,6 +188,7 @@ struct eqos_dma_regs {
 #define EQOS_DMA_SYSBUS_MODE_BLEN8			BIT(2)
 #define EQOS_DMA_SYSBUS_MODE_BLEN4			BIT(1)
 
+#define EQOS_DMA_CH0_CONTROL_DSL_SHIFT			18
 #define EQOS_DMA_CH0_CONTROL_PBLX8			BIT(16)
 
 #define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT		16
@@ -218,9 +219,21 @@ struct eqos_tegra186_regs {
 #define EQOS_AUTO_CAL_STATUS_ACTIVE			BIT(31)
 
 /* Descriptors */
+/*
+ * #if EQOS_DESCRIPTOR_SIZE < ARCH_DMA_MINALIGN fails if we use sizeof()
+ * or offsetof() to calculate descriptor size, since neither is allowed
+ * in C preprocessor macros, so just hard-code this to 16=4*sizeof(u32).
+ */
+#define EQOS_DESCRIPTOR_SIZE	16
+#define EQOS_DESCRIPTOR_PAD	((ARCH_DMA_MINALIGN - EQOS_DESCRIPTOR_SIZE) / 4)
+struct eqos_desc {
+	u32 des0;
+	u32 des1;
+	u32 des2;
+	u32 des3;
+	u32 __pad[EQOS_DESCRIPTOR_PAD];
+};
 
-#define EQOS_DESCRIPTOR_WORDS	4
-#define EQOS_DESCRIPTOR_SIZE	(EQOS_DESCRIPTOR_WORDS * 4)
 /* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
 #define EQOS_DESCRIPTOR_ALIGN	ARCH_DMA_MINALIGN
 #define EQOS_DESCRIPTORS_TX	4
@@ -249,13 +262,6 @@ struct eqos_tegra186_regs {
 #endif
 #endif
 
-struct eqos_desc {
-	u32 des0;
-	u32 des1;
-	u32 des2;
-	u32 des3;
-};
-
 #define EQOS_DESC3_OWN		BIT(31)
 #define EQOS_DESC3_FD		BIT(29)
 #define EQOS_DESC3_LD		BIT(28)
@@ -1254,7 +1260,9 @@ static int eqos_start(struct udevice *dev)
 			EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
 
 	setbits_le32(&eqos->dma_regs->ch0_control,
-		     EQOS_DMA_CH0_CONTROL_PBLX8);
+		     EQOS_DMA_CH0_CONTROL_PBLX8 |
+		     ((EQOS_DESCRIPTOR_PAD / 2) <<
+		     EQOS_DMA_CH0_CONTROL_DSL_SHIFT));
 
 	/*
 	 * Burst length must be < 1/2 FIFO size.