diff mbox series

[v4,03/12] phy: atheros: Clarify the configuration of the CLK_25M output pin

Message ID 20200506221159.1298-4-michael@walle.cc
State New
Headers show
Series phy: atheros: dt bindings and cleanup | expand

Commit Message

Michael Walle May 6, 2020, 10:11 p.m. UTC 
From: Vladimir Oltean <vladimir.oltean at nxp.com>

Also take the opportunity to use the phy_read_mmd and phy_write_mmd
convenience functions.

Signed-off-by: Vladimir Oltean <vladimir.oltean at nxp.com>
Acked-by: Joe Hershberger <joe.hershberger at ni.com>
---
 drivers/net/phy/atheros.c | 19 ++++++++++++++-----
 1 file changed, 14 insertions(+), 5 deletions(-)

Comments

Tom Rini May 7, 2020, 6:52 p.m. UTC | #1 
On Thu, May 07, 2020 at 12:11:50AM +0200, Michael Walle wrote:

> From: Vladimir Oltean <vladimir.oltean at nxp.com>
> 
> Also take the opportunity to use the phy_read_mmd and phy_write_mmd
> convenience functions.
> 
> Signed-off-by: Vladimir Oltean <vladimir.oltean at nxp.com>
> Acked-by: Joe Hershberger <joe.hershberger at ni.com>

Applied to u-boot/master, thanks!
diff mbox series

Patch

diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c
index c0c2b4db39..1da18eb5d4 100644
--- a/drivers/net/phy/atheros.c
+++ b/drivers/net/phy/atheros.c
@@ -17,6 +17,15 @@ 
 #define AR803x_DEBUG_REG_0		0x0
 #define AR803x_RGMII_RX_CLK_DLY		BIT(15)
 
+/* CLK_25M register is at MMD 7, address 0x8016 */
+#define AR803x_CLK_25M_SEL_REG		0x8016
+/* AR8035: Select frequency on CLK_25M pin through bits 4:3 */
+#define AR8035_CLK_25M_FREQ_25M		(0 | 0)
+#define AR8035_CLK_25M_FREQ_50M		(0 | BIT(3))
+#define AR8035_CLK_25M_FREQ_62M		(BIT(4) | 0)
+#define AR8035_CLK_25M_FREQ_125M	(BIT(4) | BIT(3))
+#define AR8035_CLK_25M_MASK		GENMASK(4, 3)
+
 static void ar803x_enable_rx_delay(struct phy_device *phydev, bool on)
 {
 	int regval;
@@ -78,11 +87,11 @@  static int ar8035_config(struct phy_device *phydev)
 {
 	int regval;
 
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
-	regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
-	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018));
+	/* Configure CLK_25M output clock at 125 MHz */
+	regval = phy_read_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG);
+	regval &= ~AR8035_CLK_25M_MASK; /* No surprises */
+	regval |= AR8035_CLK_25M_FREQ_125M;
+	phy_write_mmd(phydev, MDIO_MMD_AN, AR803x_CLK_25M_SEL_REG, regval);
 
 	if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) ||
 	    (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))