diff mbox series

[v2,06/13] armv8: layerscape: fix alignment for spin table

Message ID	20200601195336.3237-7-michael@walle.cc
State	Accepted
Commit	b1c41231c43b0cc6719b93fe0e0e985b7abb7f5a
Headers	show List-Id: U-Boot discussion <u-boot.lists.denx.de> From: michael at walle.cc (Michael Walle) Date: Mon, 1 Jun 2020 21:53:29 +0200 Subject: [PATCH v2 06/13] armv8: layerscape: fix alignment for spin table In-Reply-To: <20200601195336.3237-1-michael@walle.cc> References: <20200601195336.3237-1-michael@walle.cc> Message-ID: <20200601195336.3237-7-michael@walle.cc>
Series	armv8: layerscape: spin table relocation fixes and cleanups \| expand [v2,00/13] armv8: layerscape: spin table relocation fixes and cleanups [v2,01/13] armv8: layerscape: fix spin-table support [v2,02/13] armv8: layerscape: pretty print info about SMP cores [v2,03/13] armv8: layerscape: properly use CPU_RELEASE_ADDR [v2,04/13] armv8: layerscape: move spin table into own module [v2,05/13] armv8: layerscape: load function pointer using ADR [v2,06/13] armv8: layerscape: fix alignment for spin table [v2,07/13] armv8: layerscape: remove determine_mp_bootpg() [v2,08/13] armv8: layerscape: simplify get_spin_tbl_addr() calls [v2,09/13] armv8: layerscape: make wake_secondary_core_n() static [v2,10/13] armv8: layerscape: drop first .ltorg directive in spintable.S [v2,11/13] armv8: layerscape: clean exported symbols in spintable.S [v2,12/13] armv8: layerscape: relocate spin table if EFI_LOADER is enabled [v2,13/13] armv8: layerscape: rework spin table

Commit Message

Michael Walle June 1, 2020, 7:53 p.m. UTC

Fix the alignment so it will match the comments. The spin table has to
be 8 byte aligned, so ".align 3" is enough.

Signed-off-by: Michael Walle <michael at walle.cc>
---
 arch/arm/cpu/armv8/fsl-layerscape/spintable.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S
index ac9c622aee..a92f930e04 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/spintable.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/spintable.S
@@ -19,7 +19,7 @@  secondary_boot_addr:
 	.ltorg
 
 	/* Using 64 bit alignment since the spin table is accessed as data */
-	.align 4
+	.align 3
 	.global secondary_boot_code
 	/* Secondary Boot Code starts here */
 secondary_boot_code:
@@ -144,7 +144,7 @@  ENDPROC(secondary_switch_to_el1)
 	.ltorg
 
 	/* 64 bit alignment for elements accessed as data */
-	.align 4
+	.align 3
 	.global __real_cntfrq
 __real_cntfrq:
 	.quad COUNTER_FREQUENCY