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Tue, 29 Jun 2021 01:59:15 +0000 From: "Peng Fan (OSS)" To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan Subject: [PATCH V2 02/46] arm: imx: add i.MX8ULP cpu type and helper Date: Tue, 29 Jun 2021 10:31:56 +0800 Message-Id: <20210629023240.22394-3-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210629023240.22394-1-peng.fan@oss.nxp.com> References: <20210629023240.22394-1-peng.fan@oss.nxp.com> X-Originating-IP: [119.31.174.71] X-ClientProxiedBy: SG2PR06CA0088.apcprd06.prod.outlook.com (2603:1096:3:14::14) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SG2PR06CA0088.apcprd06.prod.outlook.com (2603:1096:3:14::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.19 via Frontend Transport; Tue, 29 Jun 2021 01:59:14 +0000 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 94fd3518-2927-41aa-29f5-08d93aa17fc0 X-MS-TrafficTypeDiagnostic: DB7PR04MB4633: X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:243; 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Signed-off-by: Peng Fan --- arch/arm/include/asm/arch-imx/cpu.h | 4 ++++ arch/arm/include/asm/arch-imx8ulp/sys_proto.h | 11 +++++++++++ arch/arm/include/asm/mach-imx/sys_proto.h | 1 + arch/arm/mach-imx/imx8ulp/soc.c | 11 +++++++++++ 4 files changed, 27 insertions(+) create mode 100644 arch/arm/include/asm/arch-imx8ulp/sys_proto.h create mode 100644 arch/arm/mach-imx/imx8ulp/soc.c -- 2.30.0 diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h index 267a094e5a..fe96378971 100644 --- a/arch/arm/include/asm/arch-imx/cpu.h +++ b/arch/arm/include/asm/arch-imx/cpu.h @@ -50,8 +50,12 @@ #define MXC_CPU_IMX8QXP_A0 0x90 /* dummy ID */ #define MXC_CPU_IMX8QM 0x91 /* dummy ID */ #define MXC_CPU_IMX8QXP 0x92 /* dummy ID */ + +#define MXC_CPU_IMX8ULP 0xA1 /* dummy ID */ + #define MXC_CPU_IMXRT1020 0xB4 /* dummy ID */ #define MXC_CPU_IMXRT1050 0xB6 /* dummy ID */ + #define MXC_CPU_MX7ULP 0xE1 /* Temporally hard code */ #define MXC_CPU_VF610 0xF6 /* dummy ID */ diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h new file mode 100644 index 0000000000..cab12c218e --- /dev/null +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2021 NXP + */ + +#ifndef __ARCH_IMX8ULP_SYS_PROTO_H +#define __ARCH_NMX8ULP_SYS_PROTO_H + +#include + +#endif diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h index b612189849..ad446940ff 100644 --- a/arch/arm/include/asm/mach-imx/sys_proto.h +++ b/arch/arm/include/asm/mach-imx/sys_proto.h @@ -51,6 +51,7 @@ struct bd_info; #define is_imx8md() (is_cpu_type(MXC_CPU_IMX8MD)) #define is_imx8mql() (is_cpu_type(MXC_CPU_IMX8MQL)) #define is_imx8qm() (is_cpu_type(MXC_CPU_IMX8QM)) +#define is_imx8ulp() (is_cpu_type(MXC_CPU_IMX8ULP)) #define is_imx8mm() (is_cpu_type(MXC_CPU_IMX8MM) || is_cpu_type(MXC_CPU_IMX8MML) ||\ is_cpu_type(MXC_CPU_IMX8MMD) || is_cpu_type(MXC_CPU_IMX8MMDL) || \ is_cpu_type(MXC_CPU_IMX8MMS) || is_cpu_type(MXC_CPU_IMX8MMSL)) diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c new file mode 100644 index 0000000000..b3679aefcb --- /dev/null +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include + +u32 get_cpu_rev(void) +{ + return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0; +}