Message ID | 20210719074734.29170-14-peng.fan@oss.nxp.com |
---|---|
State | Superseded |
Headers | show
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Mon, 19 Jul 2021 07:14:05 +0000 From: "Peng Fan (OSS)" <peng.fan@oss.nxp.com> To: sbabic@denx.de, festevam@gmail.com Cc: uboot-imx@nxp.com, u-boot@lists.denx.de, Peng Fan <peng.fan@nxp.com>, Ramon Fried <rfried.dev@gmail.com> Subject: [Patch V3 13/44] net: fec_mxc: support i.MX8ULP Date: Mon, 19 Jul 2021 15:47:03 +0800 Message-Id: <20210719074734.29170-14-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.30.0 In-Reply-To: <20210719074734.29170-1-peng.fan@oss.nxp.com> References: <20210719074734.29170-1-peng.fan@oss.nxp.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SGAP274CA0006.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::18) To DB6PR0402MB2760.eurprd04.prod.outlook.com (2603:10a6:4:a1::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from linux-1xn6.ap.freescale.net (119.31.174.71) by SGAP274CA0006.SGPP274.PROD.OUTLOOK.COM (2603:1096:4:b6::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4331.21 via Frontend Transport; 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imx: add i.MX8ULP support
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expand
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diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 726ad36b7c..dbdc302b29 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -330,7 +330,7 @@ config FEC_MXC_MDIO_BASE config FEC_MXC bool "FEC Ethernet controller" - depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || VF610 + depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || VF610 help This driver supports the 10/100 Fast Ethernet controller for NXP i.MX processors. diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index db2cdaf684..9bb42e5ca9 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -631,7 +631,7 @@ static int fec_init(struct eth_device *dev, struct bd_info *bd) writel(0x00000000, &fec->eth->gaddr2); /* Do not access reserved register */ - if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) { + if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp()) { /* clear MIB RAM */ for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4) writel(0, i);