Message ID | 20210719074734.29170-5-peng.fan@oss.nxp.com |
---|---|
State | Superseded |
Headers | show
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Series |
imx: add i.MX8ULP support
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expand
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diff --git a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h index cab12c218e..8894611a0f 100644 --- a/arch/arm/include/asm/arch-imx8ulp/sys_proto.h +++ b/arch/arm/include/asm/arch-imx8ulp/sys_proto.h @@ -8,4 +8,7 @@ #include <asm/mach-imx/sys_proto.h> +extern unsigned long rom_pointer[]; + +enum bt_mode get_boot_mode(void); #endif diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index b3679aefcb..e6ac5f8d25 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -3,9 +3,68 @@ * Copyright 2021 NXP */ +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> +#include <asm/mach-imx/boot_mode.h> u32 get_cpu_rev(void) { return (MXC_CPU_IMX8ULP << 12) | CHIP_REV_1_0; } + +enum bt_mode get_boot_mode(void) +{ + u32 bt0_cfg = 0; + + bt0_cfg = readl(CMC0_RBASE + 0x80); + bt0_cfg &= (BT0CFG_LPBOOT_MASK | BT0CFG_DUALBOOT_MASK); + + if (!(bt0_cfg & BT0CFG_LPBOOT_MASK)) { + /* No low power boot */ + if (bt0_cfg & BT0CFG_DUALBOOT_MASK) + return DUAL_BOOT; + else + return SINGLE_BOOT; + } + + return LOW_POWER_BOOT; +} + +#if defined(CONFIG_DISPLAY_CPUINFO) +const char *get_imx_type(u32 imxtype) +{ + return "8ULP"; +} + +int print_cpuinfo(void) +{ + u32 cpurev; + char cause[18]; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n", + get_imx_type((cpurev & 0xFF000) >> 12), + (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + + printf("Boot mode: "); + switch (get_boot_mode()) { + case LOW_POWER_BOOT: + printf("Low power boot\n"); + break; + case DUAL_BOOT: + printf("Dual boot\n"); + break; + case SINGLE_BOOT: + default: + printf("Single boot\n"); + break; + } + + return 0; +} +#endif +