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([223.178.209.222]) by smtp.gmail.com with ESMTPSA id i8-20020a17090332c800b001899c2a0ae0sm3636759plr.40.2023.02.01.05.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Feb 2023 05:59:56 -0800 (PST) From: Sumit Garg To: u-boot@lists.denx.de Cc: rfried.dev@gmail.com, hs@denx.de, joe.hershberger@ni.com, stephan@gerhold.net, mworsfold@impinj.com, lgillham@impinj.com, jbrennan@impinj.com, nicolas.dechesne@linaro.org, vinod.koul@linaro.org, daniel.thompson@linaro.org, Sumit Garg Subject: [PATCH v2 10/14] clock-snapdragon: Add clk_rcg_set_rate() with mnd_width=0 Date: Wed, 1 Feb 2023 19:28:57 +0530 Message-Id: <20230201135901.482671-11-sumit.garg@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230201135901.482671-1-sumit.garg@linaro.org> References: <20230201135901.482671-1-sumit.garg@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.6 at phobos.denx.de X-Virus-Status: Clean Add clk_rcg_set_rate() which allows to configure clocks without programming MND values. This is required for configuring I2C clocks on QCS404. Co-developed-by: Mike Worsfold Signed-off-by: Mike Worsfold Signed-off-by: Sumit Garg --- arch/arm/mach-snapdragon/clock-snapdragon.c | 24 +++++++++++++++++++++ arch/arm/mach-snapdragon/clock-snapdragon.h | 2 ++ 2 files changed, 26 insertions(+) diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c index fda7098274..0ac45dce9a 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.c +++ b/arch/arm/mach-snapdragon/clock-snapdragon.c @@ -111,6 +111,30 @@ void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, clk_bcr_update(base + regs->cmd_rcgr); } +/* root set rate for clocks with half integer and mnd_width=0 */ +void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, + int source) +{ + u32 cfg; + + /* setup src select and divider */ + cfg = readl(base + regs->cfg_rcgr); + cfg &= ~CFG_MASK; + cfg |= source & CFG_CLK_SRC_MASK; /* Select clock source */ + + /* + * Set the divider; HW permits fraction dividers (+0.5), but + * for simplicity, we will support integers only + */ + if (div) + cfg |= (2 * div - 1) & CFG_DIVIDER_MASK; + + writel(cfg, base + regs->cfg_rcgr); /* Write new clock configuration */ + + /* Inform h/w to start using the new config. */ + clk_bcr_update(base + regs->cmd_rcgr); +} + static int msm_clk_probe(struct udevice *dev) { struct msm_clk_priv *priv = dev_get_priv(dev); diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.h b/arch/arm/mach-snapdragon/clock-snapdragon.h index 2ac53b538d..c90bbefa58 100644 --- a/arch/arm/mach-snapdragon/clock-snapdragon.h +++ b/arch/arm/mach-snapdragon/clock-snapdragon.h @@ -42,5 +42,7 @@ void clk_enable_cbc(phys_addr_t cbcr); void clk_enable_vote_clk(phys_addr_t base, const struct vote_clk *vclk); void clk_rcg_set_rate_mnd(phys_addr_t base, const struct bcr_regs *regs, int div, int m, int n, int source); +void clk_rcg_set_rate(phys_addr_t base, const struct bcr_regs *regs, int div, + int source); #endif