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[206.248.184.2]) by smtp.gmail.com with ESMTPSA id z20-20020ac87f94000000b003b635a5d56csm3225447qtj.30.2023.04.23.18.15.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 23 Apr 2023 18:15:33 -0700 (PDT) From: Ralph Siemsen To: u-boot@lists.denx.de Cc: Marek Vasut , Ralph Siemsen , Marek Vasut , Nobuhiro Iwamatsu Subject: [PATCH v5 07/10] ARM: rmobile: Add support for Renesas RZ/N1 SoC Date: Sun, 23 Apr 2023 21:15:12 -0400 Message-Id: <20230424011515.1359255-8-ralph.siemsen@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230424011515.1359255-1-ralph.siemsen@linaro.org> References: <20230424011515.1359255-1-ralph.siemsen@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The RZ/N1 is a family of SoC devices from Renesas, featuring: * ARM Cortex-A7 CPU (single/dual core) and/or Cortex-M3 * Integrated SRAM up to 6MB * Integrated gigabit ethernet switch * Optional DDR2/3 controller * I2C, SPI, UART, NAND, QSPI, SDIO, USB, CAN, RTC, LCD Add basic support for this family, modeled on the existing RZA1. Signed-off-by: Ralph Siemsen --- Changes in v5: - fold mach-rzn1 into mach-rmobile arch/arm/mach-rmobile/Kconfig | 19 +++++++++++++++++++ arch/arm/mach-rmobile/Kconfig.rzn1 | 20 ++++++++++++++++++++ arch/arm/mach-rmobile/cpu_info.c | 8 ++++++++ 3 files changed, 47 insertions(+) create mode 100644 arch/arm/mach-rmobile/Kconfig.rzn1 diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig index 1ef7d68bdf..3061ccd34c 100644 --- a/arch/arm/mach-rmobile/Kconfig +++ b/arch/arm/mach-rmobile/Kconfig @@ -48,6 +48,24 @@ config RZA1 prompt "Renesas ARM SoCs RZ/A1 (32bit)" select CPU_V7A +config RZN1 + prompt "Renesas ARM SoCs RZ/N1 (32bit)" + select CPU_V7A + select ARMV7_SET_CORTEX_SMPEN if !SPL + select SPL_ARMV7_SET_CORTEX_SMPEN if SPL + select CLK + select CLK_RENESAS + select CLK_R9A06G032 + select DM + select DM_ETH + select DM_SERIAL + select PINCTRL + select PINCONF + select REGMAP + select SYSRESET + select SYSRESET_SYSCON + imply CMD_DM + endchoice config SYS_SOC @@ -56,5 +74,6 @@ config SYS_SOC source "arch/arm/mach-rmobile/Kconfig.32" source "arch/arm/mach-rmobile/Kconfig.64" source "arch/arm/mach-rmobile/Kconfig.rza1" +source "arch/arm/mach-rmobile/Kconfig.rzn1" endif diff --git a/arch/arm/mach-rmobile/Kconfig.rzn1 b/arch/arm/mach-rmobile/Kconfig.rzn1 new file mode 100644 index 0000000000..73138d69f9 --- /dev/null +++ b/arch/arm/mach-rmobile/Kconfig.rzn1 @@ -0,0 +1,20 @@ +if RZN1 + +choice + prompt "Renesas RZ/N1 Board select" + default TARGET_SCHNEIDER_RZN1 + +config TARGET_SCHNEIDER_RZN1 + bool "Schneider RZN1 board" + help + Support the Schneider RZN1D and RZN1S boards, which are based + on the Renesas RZ/N1 SoC. + +endchoice + +config SYS_SOC + default "rzn1" + +source "board/schneider/rzn1-snarc/Kconfig" + +endif diff --git a/arch/arm/mach-rmobile/cpu_info.c b/arch/arm/mach-rmobile/cpu_info.c index 7e7465a2c8..15be32af31 100644 --- a/arch/arm/mach-rmobile/cpu_info.c +++ b/arch/arm/mach-rmobile/cpu_info.c @@ -31,6 +31,7 @@ void enable_caches(void) #ifdef CONFIG_DISPLAY_CPUINFO #ifndef CONFIG_RZA1 +#ifndef CONFIG_RZN1 __weak const u8 *rzg_get_cpu_name(void) { return 0; @@ -128,6 +129,13 @@ int print_cpuinfo(void) } #else int print_cpuinfo(void) +{ + printf("CPU: Renesas Electronics RZ/N1\n"); + return 0; +} +#endif +#else +int print_cpuinfo(void) { printf("CPU: Renesas Electronics RZ/A1\n"); return 0;