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[92.17.96.230]) by smtp.gmail.com with ESMTPSA id je17-20020a05600c1f9100b0040d1450ca7esm3429723wmb.7.2023.12.19.08.04.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Dec 2023 08:04:50 -0800 (PST) From: Caleb Connolly Date: Tue, 19 Dec 2023 16:04:28 +0000 Subject: [PATCH v2 27/32] dts: dragonboard820c: use correct bindings for clocks MIME-Version: 1.0 Message-Id: <20231219-b4-qcom-common-target-v2-27-b6dd9704219e@linaro.org> References: <20231219-b4-qcom-common-target-v2-0-b6dd9704219e@linaro.org> In-Reply-To: <20231219-b4-qcom-common-target-v2-0-b6dd9704219e@linaro.org> To: Neil Armstrong , Sumit Garg , Ramon Fried , Dzmitry Sankouski , Caleb Connolly , Peng Fan , Jaehoon Chung , Rayagonda Kokatanur , Lukasz Majewski , Sean Anderson , Jorge Ramirez-Ortiz , Stephan Gerhold Cc: Marek Vasut , u-boot@lists.denx.de X-Mailer: b4 0.13-dev-4bd13 X-Developer-Signature: v=1; a=openpgp-sha256; l=1991; i=caleb.connolly@linaro.org; h=from:subject:message-id; bh=JAmaHrRcqr4XUcuqtVBcSAFI9CoP2CYlAS9vcDgswSw=; b=owGbwMvMwCFYaeA6f6eBkTjjabUkhtTG/SyWEQrX15e+SFh462+p8uYZGndONLK/7Uvrjvgk8 JbB5U1iRykLgyAHg6yYIov4iWWWTWsv22tsX3ABZg4rE8gQBi5OAZjI7weMDJ1rvfb3L6vhPVpd t643c/YL9TNGlWLN6z9MyW1Z/l807DbDX9nwd+s2nr+cUp/Rb8Z1V03Ddco9S6G+gKxvZf+6FPl ntgMA X-Developer-Key: i=caleb.connolly@linaro.org; a=openpgp; fpr=83B24DA7FE145076BC38BB250CD904EB673A7C47 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Don't use hardcoded clock IDs, use the IDs from the dt-bindings to be compatible with upstream. Signed-off-by: Caleb Connolly Reviewed-by: Neil Armstrong --- arch/arm/dts/dragonboard820c.dts | 5 +++-- drivers/clk/qcom/clock-apq8096.c | 5 +++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts index 86b7f83d36d6..282c37e28f42 100644 --- a/arch/arm/dts/dragonboard820c.dts +++ b/arch/arm/dts/dragonboard820c.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "skeleton64.dtsi" +#include / { model = "Qualcomm Technologies, Inc. DB820c"; @@ -78,7 +79,7 @@ blsp2_uart2: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x75b0000 0x1000>; - clocks = <&gcc 4>; + clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>; clock-names = "core"; pinctrl-names = "uart"; pinctrl-0 = <&blsp8_uart>; @@ -89,7 +90,7 @@ reg = <0x74a4900 0x314>, <0x74a4000 0x800>; index = <0x0>; bus-width = <4>; - clock = <&gcc 0>; + clock = <&gcc GCC_SDCC1_APPS_CLK>; clock-frequency = <200000000>; }; diff --git a/drivers/clk/qcom/clock-apq8096.c b/drivers/clk/qcom/clock-apq8096.c index 1e6fdb5cd42d..a4731613c5e0 100644 --- a/drivers/clk/qcom/clock-apq8096.c +++ b/drivers/clk/qcom/clock-apq8096.c @@ -13,6 +13,7 @@ #include #include #include +#include #include "clock-qcom.h" @@ -107,10 +108,10 @@ static ulong apq8096_clk_set_rate(struct clk *clk, ulong rate) struct msm_clk_priv *priv = dev_get_priv(clk->dev); switch (clk->id) { - case 0: /* SDC1 */ + case GCC_SDCC1_APPS_CLK: /* SDC1 */ return clk_init_sdc(priv, rate); break; - case 4: /*UART2*/ + case GCC_BLSP2_UART2_APPS_CLK: /*UART2*/ return clk_init_uart(priv); default: return 0;