diff mbox series

[v4,03/39] mmc: msm_sdhci: use modern clock handling

Message ID 20240215-b4-qcom-common-target-v4-3-ed06355c634a@linaro.org
State Superseded
Headers show
Series Qualcomm generic board support | expand

Commit Message

Caleb Connolly Feb. 15, 2024, 8:52 p.m. UTC 
Use the clk_* helper functions and the correct property name for clocks.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
---
 drivers/mmc/msm_sdhci.c | 69 +++++++++++++++++++++++++++++++++----------------
 1 file changed, 47 insertions(+), 22 deletions(-)

Comments

Sumit Garg Feb. 20, 2024, 5:42 a.m. UTC | #1 
On Fri, 16 Feb 2024 at 02:22, Caleb Connolly <caleb.connolly@linaro.org> wrote:
>
> Use the clk_* helper functions and the correct property name for clocks.
>
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Caleb Connolly <caleb.connolly@linaro.org>
> ---
>  drivers/mmc/msm_sdhci.c | 69 +++++++++++++++++++++++++++++++++----------------
>  1 file changed, 47 insertions(+), 22 deletions(-)
>

Reviewed-by: Sumit Garg <sumit.garg@linaro.org>

-Sumit

> diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
> index fe1e754bfde0..b63538fce20c 100644
> --- a/drivers/mmc/msm_sdhci.c
> +++ b/drivers/mmc/msm_sdhci.c
> @@ -44,6 +44,7 @@ struct msm_sdhc_plat {
>  struct msm_sdhc {
>         struct sdhci_host host;
>         void *base;
> +       struct clk_bulk clks;
>  };
>
>  struct msm_sdhc_variant_info {
> @@ -54,35 +55,57 @@ DECLARE_GLOBAL_DATA_PTR;
>
>  static int msm_sdc_clk_init(struct udevice *dev)
>  {
> -       int node = dev_of_offset(dev);
> -       uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
> -                                       400000);
> -       uint clkd[2]; /* clk_id and clk_no */
> -       int clk_offset;
> -       struct udevice *clk_dev;
> -       struct clk clk;
> -       int ret;
> +       struct msm_sdhc *prv = dev_get_priv(dev);
> +       ofnode node = dev_ofnode(dev);
> +       uint clk_rate;
> +       int ret, i = 0, n_clks;
> +       const char *clk_name;
>
> -       ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
> +       ret = ofnode_read_u32(node, "clock-frequency", &clk_rate);
>         if (ret)
> -               return ret;
> +               clk_rate = 400000;
>
> -       clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
> -       if (clk_offset < 0)
> -               return clk_offset;
> -
> -       ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
> -       if (ret)
> +       ret = clk_get_bulk(dev, &prv->clks);
> +       if (ret) {
> +               log_warning("Couldn't get mmc clocks: %d\n", ret);
>                 return ret;
> +       }
>
> -       clk.id = clkd[1];
> -       ret = clk_request(clk_dev, &clk);
> -       if (ret < 0)
> +       ret = clk_enable_bulk(&prv->clks);
> +       if (ret) {
> +               log_warning("Couldn't enable mmc clocks: %d\n", ret);
>                 return ret;
> +       }
>
> -       ret = clk_set_rate(&clk, clk_rate);
> -       if (ret < 0)
> -               return ret;
> +       /* If clock-names is unspecified, then the first clock is the core clock */
> +       if (!ofnode_get_property(node, "clock-names", &n_clks)) {
> +               if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
> +                       log_warning("Couldn't set core clock rate: %d\n", ret);
> +                       return -EINVAL;
> +               }
> +       }
> +
> +       /* Find the index of the "core" clock */
> +       while (i < n_clks) {
> +               ofnode_read_string_index(node, "clock-names", i, &clk_name);
> +               if (!strcmp(clk_name, "core"))
> +                       break;
> +               i++;
> +       }
> +
> +       if (i >= prv->clks.count) {
> +               log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
> +                      prv->clks.count);
> +               return -EINVAL;
> +       }
> +
> +       /* The clock is already enabled by the clk_bulk above */
> +       ret = clk_set_rate(&prv->clks.clks[i], clk_rate);
> +       /* If we get a rate of 0 then something has probably gone wrong. */
> +       if (ret == 0) {
> +               log_warning("Couldn't set core clock rate to %u! Driver returned rate of 0\n", clk_rate);
> +               return -EINVAL;
> +       }
>
>         return 0;
>  }
> @@ -187,6 +210,8 @@ static int msm_sdc_remove(struct udevice *dev)
>         if (!var_info->mci_removed)
>                 writel(0, priv->base + SDCC_MCI_HC_MODE);
>
> +       clk_release_bulk(&priv->clks);
> +
>         return 0;
>  }
>
>
> --
> 2.43.1
>
Dan Carpenter Feb. 20, 2024, 7:20 a.m. UTC | #2 
On Thu, Feb 15, 2024 at 08:52:21PM +0000, Caleb Connolly wrote:
>  static int msm_sdc_clk_init(struct udevice *dev)
>  {
> -	int node = dev_of_offset(dev);
> -	uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
> -					400000);
> -	uint clkd[2]; /* clk_id and clk_no */
> -	int clk_offset;
> -	struct udevice *clk_dev;
> -	struct clk clk;
> -	int ret;
> +	struct msm_sdhc *prv = dev_get_priv(dev);
> +	ofnode node = dev_ofnode(dev);
> +	uint clk_rate;
> +	int ret, i = 0, n_clks;
> +	const char *clk_name;
>  
> -	ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
> +	ret = ofnode_read_u32(node, "clock-frequency", &clk_rate);
>  	if (ret)
> -		return ret;
> +		clk_rate = 400000;
>  
> -	clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
> -	if (clk_offset < 0)
> -		return clk_offset;
> -
> -	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
> -	if (ret)
> +	ret = clk_get_bulk(dev, &prv->clks);
> +	if (ret) {
> +		log_warning("Couldn't get mmc clocks: %d\n", ret);
>  		return ret;
> +	}
>  
> -	clk.id = clkd[1];
> -	ret = clk_request(clk_dev, &clk);
> -	if (ret < 0)
> +	ret = clk_enable_bulk(&prv->clks);
> +	if (ret) {
> +		log_warning("Couldn't enable mmc clocks: %d\n", ret);
>  		return ret;
> +	}
>  
> -	ret = clk_set_rate(&clk, clk_rate);
> -	if (ret < 0)
> -		return ret;
> +	/* If clock-names is unspecified, then the first clock is the core clock */
> +	if (!ofnode_get_property(node, "clock-names", &n_clks)) {
> +		if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
> +			log_warning("Couldn't set core clock rate: %d\n", ret);

s/ret/clk_rate/

regards,
dan carpenter

> +			return -EINVAL;
> +		}
> +	}
> +
> +	/* Find the index of the "core" clock */
> +	while (i < n_clks) {
> +		ofnode_read_string_index(node, "clock-names", i, &clk_name);
> +		if (!strcmp(clk_name, "core"))
> +			break;
> +		i++;
> +	}
> +
> +	if (i >= prv->clks.count) {
> +		log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
> +		       prv->clks.count);
> +		return -EINVAL;
> +	}
> +
> +	/* The clock is already enabled by the clk_bulk above */
> +	ret = clk_set_rate(&prv->clks.clks[i], clk_rate);
> +	/* If we get a rate of 0 then something has probably gone wrong. */
> +	if (ret == 0) {
> +		log_warning("Couldn't set core clock rate to %u! Driver returned rate of 0\n", clk_rate);
> +		return -EINVAL;
> +	}
>  
>  	return 0;
>  }
diff mbox series

Patch

diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index fe1e754bfde0..b63538fce20c 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -44,6 +44,7 @@  struct msm_sdhc_plat {
 struct msm_sdhc {
 	struct sdhci_host host;
 	void *base;
+	struct clk_bulk clks;
 };
 
 struct msm_sdhc_variant_info {
@@ -54,35 +55,57 @@  DECLARE_GLOBAL_DATA_PTR;
 
 static int msm_sdc_clk_init(struct udevice *dev)
 {
-	int node = dev_of_offset(dev);
-	uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
-					400000);
-	uint clkd[2]; /* clk_id and clk_no */
-	int clk_offset;
-	struct udevice *clk_dev;
-	struct clk clk;
-	int ret;
+	struct msm_sdhc *prv = dev_get_priv(dev);
+	ofnode node = dev_ofnode(dev);
+	uint clk_rate;
+	int ret, i = 0, n_clks;
+	const char *clk_name;
 
-	ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
+	ret = ofnode_read_u32(node, "clock-frequency", &clk_rate);
 	if (ret)
-		return ret;
+		clk_rate = 400000;
 
-	clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
-	if (clk_offset < 0)
-		return clk_offset;
-
-	ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
-	if (ret)
+	ret = clk_get_bulk(dev, &prv->clks);
+	if (ret) {
+		log_warning("Couldn't get mmc clocks: %d\n", ret);
 		return ret;
+	}
 
-	clk.id = clkd[1];
-	ret = clk_request(clk_dev, &clk);
-	if (ret < 0)
+	ret = clk_enable_bulk(&prv->clks);
+	if (ret) {
+		log_warning("Couldn't enable mmc clocks: %d\n", ret);
 		return ret;
+	}
 
-	ret = clk_set_rate(&clk, clk_rate);
-	if (ret < 0)
-		return ret;
+	/* If clock-names is unspecified, then the first clock is the core clock */
+	if (!ofnode_get_property(node, "clock-names", &n_clks)) {
+		if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
+			log_warning("Couldn't set core clock rate: %d\n", ret);
+			return -EINVAL;
+		}
+	}
+
+	/* Find the index of the "core" clock */
+	while (i < n_clks) {
+		ofnode_read_string_index(node, "clock-names", i, &clk_name);
+		if (!strcmp(clk_name, "core"))
+			break;
+		i++;
+	}
+
+	if (i >= prv->clks.count) {
+		log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
+		       prv->clks.count);
+		return -EINVAL;
+	}
+
+	/* The clock is already enabled by the clk_bulk above */
+	ret = clk_set_rate(&prv->clks.clks[i], clk_rate);
+	/* If we get a rate of 0 then something has probably gone wrong. */
+	if (ret == 0) {
+		log_warning("Couldn't set core clock rate to %u! Driver returned rate of 0\n", clk_rate);
+		return -EINVAL;
+	}
 
 	return 0;
 }
@@ -187,6 +210,8 @@  static int msm_sdc_remove(struct udevice *dev)
 	if (!var_info->mci_removed)
 		writel(0, priv->base + SDCC_MCI_HC_MODE);
 
+	clk_release_bulk(&priv->clks);
+
 	return 0;
 }