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[2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id 4fb4d7f45d1cf-5bebc0b78d7si8121192a12.575.2024.08.21.04.01.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Aug 2024 04:01:04 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id B9EB988B52; Wed, 21 Aug 2024 12:59:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 1F05088B4C; Wed, 21 Aug 2024 12:59:47 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED, SPF_HELO_NONE,SPF_SOFTFAIL,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id E8FC088DA4 for ; Wed, 21 Aug 2024 12:59:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sughosh.ganu@linaro.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7C1F0DA7; Wed, 21 Aug 2024 04:00:10 -0700 (PDT) Received: from a079122.blr.arm.com (a079122.arm.com [10.162.17.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1AAC83F73B; Wed, 21 Aug 2024 03:59:40 -0700 (PDT) From: Sughosh Ganu To: u-boot@lists.denx.de Cc: Simon Glass , Tom Rini , Ilias Apalodimas , Heinrich Schuchardt , Marek Vasut , Mark Kettenis , Michal Simek , Patrick DELAUNAY , Patrice CHOTARD , Sughosh Ganu Subject: [PATCH v3 12/27] lmb: remove the lmb_init_and_reserve() function Date: Wed, 21 Aug 2024 16:28:24 +0530 Message-Id: <20240821105839.2870293-13-sughosh.ganu@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240821105839.2870293-1-sughosh.ganu@linaro.org> References: <20240821105839.2870293-1-sughosh.ganu@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean With the changes to make the LMB reservations persistent, the common memory regions are being added during board init. Remove the now superfluous lmb_init_and_reserve() function. Signed-off-by: Sughosh Ganu Reviewed-by: Simon Glass --- Changes since V2: None arch/arm/mach-apple/board.c | 2 -- arch/arm/mach-snapdragon/board.c | 2 -- arch/arm/mach-stm32mp/stm32mp1/cpu.c | 3 --- cmd/bdinfo.c | 1 - cmd/load.c | 2 -- fs/fs.c | 1 - include/lmb.h | 1 - lib/lmb.c | 13 ------------- net/tftp.c | 2 -- net/wget.c | 2 -- 10 files changed, 29 deletions(-) diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 213390d6e8..0b6d290b8a 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -775,8 +775,6 @@ int board_late_init(void) { u32 status = 0; - lmb_init_and_reserve(gd->bd, (void *)gd->fdt_blob); - /* somewhat based on the Linux Kernel boot requirements: * align by 2M and maximal FDT size 2M */ diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c index a63c8bec45..22a7d2a637 100644 --- a/arch/arm/mach-snapdragon/board.c +++ b/arch/arm/mach-snapdragon/board.c @@ -282,8 +282,6 @@ int board_late_init(void) { u32 status = 0; - lmb_init_and_reserve(gd->bd, (void *)gd->fdt_blob); - /* We need to be fairly conservative here as we support boards with just 1G of TOTAL RAM */ status |= env_set_hex("kernel_addr_r", addr_alloc(SZ_128M)); status |= env_set_hex("ramdisk_addr_r", addr_alloc(SZ_128M)); diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index a913737342..64480da9f8 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -141,9 +141,6 @@ int mach_cpu_init(void) void enable_caches(void) { - /* parse device tree when data cache is still activated */ - lmb_init_and_reserve(gd->bd, (void *)gd->fdt_blob); - /* I-cache is already enabled in start.S: icache_enable() not needed */ /* deactivate the data cache, early enabled in arch_cpu_init() */ diff --git a/cmd/bdinfo.c b/cmd/bdinfo.c index b31e0208df..3c40dee143 100644 --- a/cmd/bdinfo.c +++ b/cmd/bdinfo.c @@ -162,7 +162,6 @@ static int bdinfo_print_all(struct bd_info *bd) bdinfo_print_num_l("multi_dtb_fit", (ulong)gd->multi_dtb_fit); #endif if (IS_ENABLED(CONFIG_LMB) && gd->fdt_blob) { - lmb_init_and_reserve(gd->bd, (void *)gd->fdt_blob); lmb_dump_all_force(); if (IS_ENABLED(CONFIG_OF_REAL)) printf("devicetree = %s\n", fdtdec_get_srcname()); diff --git a/cmd/load.c b/cmd/load.c index 56da3a4c5d..20d802502a 100644 --- a/cmd/load.c +++ b/cmd/load.c @@ -153,8 +153,6 @@ static ulong load_serial(long offset) int line_count = 0; long ret; - lmb_init_and_reserve(gd->bd, (void *)gd->fdt_blob); - while (read_record(record, SREC_MAXRECLEN + 1) >= 0) { type = srec_decode(record, &binlen, &addr, binbuf); diff --git a/fs/fs.c b/fs/fs.c index 3fb00590be..4bc28d1dff 100644 --- a/fs/fs.c +++ b/fs/fs.c @@ -549,7 +549,6 @@ static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset, if (len && len < read_len) read_len = len; - lmb_init_and_reserve(gd->bd, (void *)gd->fdt_blob); lmb_dump_all(); if (lmb_alloc_addr(addr, read_len) == addr) diff --git a/include/lmb.h b/include/lmb.h index 3f766caa45..6d41672216 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -63,7 +63,6 @@ struct lmb { */ int lmb_init(void); -void lmb_init_and_reserve(struct bd_info *bd, void *fdt_blob); void lmb_init_and_reserve_range(phys_addr_t base, phys_size_t size, void *fdt_blob); diff --git a/lib/lmb.c b/lib/lmb.c index f94f620a37..83d3512a02 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -227,19 +227,6 @@ static void lmb_reserve_common(void *fdt_blob) efi_lmb_reserve(); } -/* Initialize the struct, add memory and call arch/board reserve functions */ -void lmb_init_and_reserve(struct bd_info *bd, void *fdt_blob) -{ - int i; - - for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { - if (bd->bi_dram[i].size) - lmb_add(bd->bi_dram[i].start, bd->bi_dram[i].size); - } - - lmb_reserve_common(fdt_blob); -} - /* Initialize the struct, add memory and call arch/board reserve functions */ void lmb_init_and_reserve_range(phys_addr_t base, phys_size_t size, void *fdt_blob) diff --git a/net/tftp.c b/net/tftp.c index 99b2ab9fca..b5d227d8bc 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -718,8 +718,6 @@ static int tftp_init_load_addr(void) if (CONFIG_IS_ENABLED(LMB)) { phys_size_t max_size; - lmb_init_and_reserve(gd->bd, (void *)gd->fdt_blob); - max_size = lmb_get_free_size(image_load_addr); if (!max_size) return -1; diff --git a/net/wget.c b/net/wget.c index 241465b9b4..4a168641c6 100644 --- a/net/wget.c +++ b/net/wget.c @@ -75,8 +75,6 @@ static int wget_init_load_size(void) { phys_size_t max_size; - lmb_init_and_reserve(gd->bd, (void *)gd->fdt_blob); - max_size = lmb_get_free_size(image_load_addr); if (!max_size) return -1;