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[2a01:238:438b:c500:173d:9f52:ddab:ee01]) by mx.google.com with ESMTPS id e9e14a558f8ab-3a3afe0d91csi33364395ab.145.2024.10.13.03.57.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 13 Oct 2024 03:57:27 -0700 (PDT) Received-SPF: pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; Authentication-Results: mx.google.com; spf=pass (google.com: domain of u-boot-bounces@lists.denx.de designates 2a01:238:438b:c500:173d:9f52:ddab:ee01 as permitted sender) smtp.mailfrom=u-boot-bounces@lists.denx.de; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A267E88F3C; Sun, 13 Oct 2024 12:56:16 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 6EB3888F57; Sun, 13 Oct 2024 12:56:15 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_VALIDITY_CERTIFIED_BLOCKED, RCVD_IN_VALIDITY_RPBL_BLOCKED,SPF_HELO_NONE,SPF_SOFTFAIL autolearn=no autolearn_force=no version=3.4.2 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by phobos.denx.de (Postfix) with ESMTP id 083B288F4D for ; Sun, 13 Oct 2024 12:56:13 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sughosh.ganu@linaro.org Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1ACBB1063; Sun, 13 Oct 2024 03:56:42 -0700 (PDT) Received: from a079122.blr.arm.com (a079122.arm.com [10.162.17.48]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E823A3F71E; Sun, 13 Oct 2024 03:56:09 -0700 (PDT) From: Sughosh Ganu To: u-boot@lists.denx.de Cc: Ilias Apalodimas , Heinrich Schuchardt , Simon Glass , Tom Rini , Caleb Connolly , Jonas Karlman , Sughosh Ganu Subject: [PATCH v3 10/15] lmb: allow for boards to specify memory map Date: Sun, 13 Oct 2024 16:25:17 +0530 Message-Id: <20241013105522.391414-11-sughosh.ganu@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20241013105522.391414-1-sughosh.ganu@linaro.org> References: <20241013105522.391414-1-sughosh.ganu@linaro.org> MIME-Version: 1.0 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean Some architectures have special or unique aspects which need consideration when adding memory ranges to the list of available memory map. Enable this config in such scenarios which allow architectures and boards to define their own memory map. Signed-off-by: Sughosh Ganu --- Changes since V2: None include/lmb.h | 2 ++ lib/Kconfig | 18 ++++++++++++++++++ lib/lmb.c | 3 +++ 3 files changed, 23 insertions(+) diff --git a/include/lmb.h b/include/lmb.h index 92e9aead76..a63c75eda8 100644 --- a/include/lmb.h +++ b/include/lmb.h @@ -166,6 +166,8 @@ long lmb_free(phys_addr_t base, phys_size_t size); void lmb_dump_all(void); void lmb_dump_all_force(void); +void lmb_arch_add_memory(void); + struct lmb *lmb_get(void); int lmb_push(struct lmb *store); void lmb_pop(struct lmb *store); diff --git a/lib/Kconfig b/lib/Kconfig index 61452f7ac9..100c4e5c25 100644 --- a/lib/Kconfig +++ b/lib/Kconfig @@ -1132,6 +1132,24 @@ config SPL_LMB SPL. This will require a malloc() implementation for defining the data structures needed for maintaining the LMB memory map. +config LMB_ARCH_MEM_MAP + bool "Add an architecture specific memory map" + depends on LMB + help + Some architectures have special or unique aspects which need + consideration when adding memory ranges to the list of available + memory map. Enable this config in such scenarios which allow + architectures and boards to define their own memory map. + +config SPL_LMB_ARCH_MEM_MAP + bool "Add an architecture specific memory map" + depends on SPL_LMB + help + Some architectures have special or unique scenarios which need + consideration when adding memory ranges to the list of available + memory map. Enable this config in such scenarios which allow + architectures and boards to define their own memory map. + config PHANDLE_CHECK_SEQ bool "Enable phandle check while getting sequence number" help diff --git a/lib/lmb.c b/lib/lmb.c index a567c02784..c08ab2223a 100644 --- a/lib/lmb.c +++ b/lib/lmb.c @@ -331,6 +331,9 @@ void lmb_add_memory(void) u64 ram_top = gd->ram_top; struct bd_info *bd = gd->bd; + if (CONFIG_IS_ENABLED(LMB_ARCH_MEM_MAP)) + return lmb_arch_add_memory(); + /* Assume a 4GB ram_top if not defined */ if (!ram_top) ram_top = 0x100000000ULL;