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[176.92.191.135]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e4c3fb5927sm4257231a12.53.2025.03.01.08.50.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Mar 2025 08:50:07 -0800 (PST) From: Ilias Apalodimas To: xypron.glpk@gmx.de, mark.kettenis@xs4all.nl Cc: Ilias Apalodimas , Alexey Brodkin , Eugeniy Paltsev , Tom Rini , Huan Wang , Angelo Dureghello , Thomas Chou , Rick Chen , Leo , Marek Vasut , Nobuhiro Iwamatsu , Max Filippov , Simon Glass , Sughosh Ganu , Caleb Connolly , Sam Protsenko , Neil Armstrong , Jerome Forissier , =?utf-8?q?Pierre-Cl=C3=A9me?= =?utf-8?q?nt_Tosi?= , Richard Henderson , Sam Edwards , Peter Hoyes , Andre Przywara , Patrick Rudolph , Mayuresh Chitale , Mattijs Korpershoek , Stefan Roese , Jiaxun Yang , Alex Shumsky , Joshua Watt , Jagan Teki , Evgeny Bachinin , Christian Marangi , Michal Simek , Rasmus Villemoes , Jonas Jelonek , uboot-snps-arc@synopsys.com, u-boot@lists.denx.de Subject: [PATCH v4 4/6] arm64: mmu_change_region_attr() add an option not to break PTEs Date: Sat, 1 Mar 2025 18:49:02 +0200 Message-ID: <20250301164922.397441-5-ilias.apalodimas@linaro.org> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250301164922.397441-1-ilias.apalodimas@linaro.org> References: <20250301164922.397441-1-ilias.apalodimas@linaro.org> MIME-Version: 1.0 X-Mailman-Approved-At: Sun, 02 Mar 2025 13:40:23 +0100 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.8 at phobos.denx.de X-Virus-Status: Clean The ARM ARM on section 8.17.1 describes the cases where break-before-make is required when changing live page tables. Since we can use this function to tweak block and page permssions, where BBM is not required add an extra argument to the function. While at it add a function description. Signed-off-by: Ilias Apalodimas --- arch/arm/cpu/armv8/cache_v8.c | 48 ++++++++++++++++++++--------------- arch/arm/include/asm/system.h | 18 +++++++++++++ 2 files changed, 46 insertions(+), 20 deletions(-) diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c index c4b3da4a8da7..29100913bc82 100644 --- a/arch/arm/cpu/armv8/cache_v8.c +++ b/arch/arm/cpu/armv8/cache_v8.c @@ -967,61 +967,69 @@ void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size, flush_dcache_range(real_start, real_start + real_size); } -/* - * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits. - * The procecess is break-before-make. The target region will be marked as - * invalid during the process of changing. - */ -void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t siz, u64 attrs) { int level; u64 r, size, start; - start = addr; - size = siz; /* * Loop through the address range until we find a page granule that fits - * our alignment constraints, then set it to "invalid". + * our alignment constraints, then set it to the new cache attributes */ + start = addr; + size = siz; while (size > 0) { for (level = 1; level < 4; level++) { - /* Set PTE to fault */ - r = set_one_region(start, size, PTE_TYPE_FAULT, true, - level); + /* Set PTE to new attributes */ + r = set_one_region(start, size, attrs, true, level); if (r) { - /* PTE successfully invalidated */ + /* PTE successfully updated */ size -= r; start += r; break; } } } - flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); __asm_invalidate_tlb_all(); +} + +/* + * Modify MMU table for a region with updated PXN/UXN/Memory type/valid bits. + * The procecess is break-before-make. The target region will be marked as + * invalid during the process of changing. + */ +void mmu_change_region_attr(phys_addr_t addr, size_t siz, u64 attrs) +{ + int level; + u64 r, size, start; + start = addr; + size = siz; /* * Loop through the address range until we find a page granule that fits - * our alignment constraints, then set it to the new cache attributes + * our alignment constraints, then set it to "invalid". */ - start = addr; - size = siz; while (size > 0) { for (level = 1; level < 4; level++) { - /* Set PTE to new attributes */ - r = set_one_region(start, size, attrs, true, level); + /* Set PTE to fault */ + r = set_one_region(start, size, PTE_TYPE_FAULT, true, + level); if (r) { - /* PTE successfully updated */ + /* PTE successfully invalidated */ size -= r; start += r; break; } } } + flush_dcache_range(gd->arch.tlb_addr, gd->arch.tlb_addr + gd->arch.tlb_size); __asm_invalidate_tlb_all(); + + mmu_change_region_attr_nobreak(addr, siz, attrs); } #else /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 091082281c73..849b3d0efb7a 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -303,8 +303,26 @@ void flush_l3_cache(void); * @emerg: Also map the region in the emergency table */ void mmu_map_region(phys_addr_t start, u64 size, bool emerg); + +/** + * mmu_change_region_attr() - change a mapped region attributes + * + * @start: Start address of the region + * @size: Size of the region + * @aatrs: New attributes + */ void mmu_change_region_attr(phys_addr_t start, size_t size, u64 attrs); +/** + * mmu_change_region_attr_nobreak() - change a mapped region attributes without doing + * break-before-make + * + * @start: Start address of the region + * @size: Size of the region + * @aatrs: New attributes + */ +void mmu_change_region_attr_nobreak(phys_addr_t addr, size_t size, u64 attrs); + /* * smc_call() - issue a secure monitor call *