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[198.145.21.10]) by mx.google.com with ESMTPS id h10si3138046pgq.545.2017.11.17.11.04.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:39 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=aZT9vAWZ; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 59F722035BB26; Fri, 17 Nov 2017 11:00:27 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::242; helo=mail-wr0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x242.google.com (mail-wr0-x242.google.com [IPv6:2a00:1450:400c:c0c::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D068F21B00DC1 for ; Fri, 17 Nov 2017 11:00:25 -0800 (PST) Received: by mail-wr0-x242.google.com with SMTP id k61so2930137wrc.4 for ; Fri, 17 Nov 2017 11:04:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=ZjFT/bvDbG8FHNMEYfljLOvEYtQimyaHKB0SkphQBvQ=; b=aZT9vAWZqgKVtDMswEXkT63kV7KwmEbBrCgi45kiVwYbLje8RZEsTrecB5XwLgvEI3 dGfUie9kyLOQVkKCkyORJoVSVYFmzeVswfPMDZIENASig+93/8R1uDNh7M4ZWA8Pzyyy ROOWDsD4lXbTkC5YWs3bKVb4QWVElWvG178v0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=ZjFT/bvDbG8FHNMEYfljLOvEYtQimyaHKB0SkphQBvQ=; b=tx8uy51awJWREsGLEMHcPia90+spk7XrKbpB6gwqxh0+3AP1r32S55Xxlyg7Xva5mr Dc3TXVfkkk+7UGs4f7bsPiQLCyPwUdKq5qeM8FufEt37wRt2yqlssrqq7w+zNqjmmfw+ L4CtSPfHrIkZbFAuYHS4h/vnzQtmV6dmZp96dToixRhB3fKq+d0tiVnN++GElWBciO0i ev3XTS8PmXNWg81JBY2Z88198Ph4eBTPmVMwKdwz9w0oyTJ8h0X0WiNbUfeARYD040Jz Thp6Sb7uo3PrqjWJm487MGobsS12R4j6SfCUvFv9A3z4owjJJcnCMz3+s0Kr1XJj8H5V R4Xw== X-Gm-Message-State: AJaThX4Aj/rqUhNgpXQX8cnPzDiiU4ICrfAxXyfCYHXJ7vkGK8dp3+ly vgs3mbD0yO9dK/dV5W05AMHXKHN3ZlQ= X-Received: by 10.223.184.171 with SMTP id i40mr261232wrf.124.1510945474800; Fri, 17 Nov 2017 11:04:34 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id c54sm7139022wra.84.2017.11.17.11.04.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Nov 2017 11:04:33 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org Date: Fri, 17 Nov 2017 19:04:17 +0000 Message-Id: <20171117190423.19511-1-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 Subject: [edk2] [PATCH edk2-platforms v5 0/6] add remaining support for Socionext SynQuacer X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" These are the remaining patches that still need review after the majority of the Socionext SynQuacer support patches were merged. Changes since v4: - minor changes, please see the notes in the individual patches Changes since v3: - remove ACPI support for now, we can add it on top if we manage to sort out all the SoC quirks that make it difficult to have full support under ACPI - add RTC support to DeveloperBox - add eMMC support to SynQuacerEvalBoard - incorporate review feedback on the SPI NOR driver (which was possible after noticing that I did in fact have a manual for this IP) - map NOR and EEPROM as writeback cacheable non-shareable; this allows the split FV hack to be reverted, and improves boot time considerably - some other minor changes have been applied, these have been added to the individual patches as notes Changes since v2: - converted NETSEC driver to UEFI driver model - added a platform DXE driver that declares the non-discoverable NETSEC device for the UEFI driver model driver to bind to - remove hardcoded DRAM information - everything is now retrieved from ARM Trusted Firmware - added DT descriptions of the GPIO and interrupt controller IP blocks - addressed various style issues and merge errors highlighted by Leif Ard Biesheuvel (6): Silicon/SynQuacer: implement 'clear NVRAM' feature using a DIP switch Silicon/SynQuacer: add DT description of the SDHCI controller Silicon/Socionext: implement I2C master protocol for SynQuacer I2C Silicon/NXP: add RTC support library for PCF8563 I2C IP Platform/DeveloperBox: wire up RTC support Platform/SynQuacerEvalBoard: add eMMC driver stack Platform/Socionext/DeveloperBox/DeveloperBox.dsc | 13 +- Platform/Socionext/DeveloperBox/DeveloperBox.fdf | 6 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.dsc | 12 + Platform/Socionext/SynQuacerEvalBoard/SynQuacerEvalBoard.fdf | 8 + Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c | 402 +++++++++++++ Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec | 31 ++ Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf | 52 ++ Silicon/Socionext/SynQuacer/DeviceTree/SynQuacer.dtsi | 27 + Silicon/Socionext/SynQuacer/DeviceTree/SynQuacerEvalBoard.dts | 4 + Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c | 201 +++++++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.c | 88 ++- Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h | 37 ++ Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.inf | 11 +- Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c | 185 ++++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/DriverBinding.c | 238 ++++++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c | 588 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.h | 162 ++++++ Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf | 59 ++ Silicon/Socionext/SynQuacer/Include/Platform/MemoryMap.h | 8 + Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 4 + Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.c | 30 +- Silicon/Socionext/SynQuacer/Library/SynQuacerPlatformPeiLib/SynQuacerPlatformPeiLib.inf | 6 + Silicon/Socionext/SynQuacer/SynQuacer.dec | 8 + 23 files changed, 2160 insertions(+), 20 deletions(-) create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.c create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.dec create mode 100644 Silicon/NXP/Library/Pcf8563RealTimeClockLib/Pcf8563RealTimeClockLib.inf create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/Emmc.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/PlatformDxe/PlatformDxe.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/ComponentName.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/DriverBinding.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.c create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.h create mode 100644 Silicon/Socionext/SynQuacer/Drivers/SynQuacerI2cDxe/SynQuacerI2cDxe.inf -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel Reviewed-by: Leif Lindholm