From patchwork Tue Mar 8 14:20:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laszlo Ersek X-Patchwork-Id: 63682 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp2054716lbc; Tue, 8 Mar 2016 06:20:19 -0800 (PST) X-Received: by 10.66.255.39 with SMTP id an7mr42018940pad.2.1457446817600; Tue, 08 Mar 2016 06:20:17 -0800 (PST) Return-Path: Received: from ml01.01.org (ml01.01.org. [2001:19d0:306:5::1]) by mx.google.com with ESMTPS id y8si4982241pas.240.2016.03.08.06.20.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 Mar 2016 06:20:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 3A2811A1F36; Tue, 8 Mar 2016 06:20:30 -0800 (PST) X-Original-To: edk2-devel@ml01.01.org Delivered-To: edk2-devel@ml01.01.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A25991A1E8E for ; Tue, 8 Mar 2016 06:20:29 -0800 (PST) Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (Postfix) with ESMTPS id E0AA244594; Tue, 8 Mar 2016 14:20:15 +0000 (UTC) Received: from lacos-laptop-7.usersys.redhat.com (ovpn-113-59.phx2.redhat.com [10.3.113.59]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id u28EK7nV018352; Tue, 8 Mar 2016 09:20:14 -0500 From: Laszlo Ersek To: edk2-devel@ml01.01.org Date: Tue, 8 Mar 2016 15:20:00 +0100 Message-Id: <1457446804-18892-3-git-send-email-lersek@redhat.com> In-Reply-To: <1457446804-18892-1-git-send-email-lersek@redhat.com> References: <1457446804-18892-1-git-send-email-lersek@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 Cc: Marcel Apfelbaum , Jordan Justen , Gabriel Somlo , =?UTF-8?q?Micha=C5=82=20Zegan?= Subject: [edk2] [PATCH v2 2/6] OvmfPkg: PlatformPei: lower the 32-bit PCI MMIO base to 2GB on Q35 X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.17 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Gerd has advised us that long term support Q35 machine types have no low RAM above 2GB, hence we should utilize the [2GB, 3GB) gap -- that we currently leave unused -- for MMIO. (Plus, later in this series, for the PCIEXBAR too.) Cc: Gabriel Somlo Cc: Gerd Hoffmann Cc: Jordan Justen Cc: Marcel Apfelbaum Cc: Michał Zegan Ref: https://github.com/tianocore/edk2/issues/32 Ref: http://thread.gmane.org/gmane.comp.bios.edk2.devel/8707/focus=8817 Suggested-by: Gerd Hoffmann Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek --- Notes: v2: - new in v2 OvmfPkg/PlatformPei/Platform.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/OvmfPkg/PlatformPei/Platform.c b/OvmfPkg/PlatformPei/Platform.c index 7d0941209f25..8e4da41001e1 100644 --- a/OvmfPkg/PlatformPei/Platform.c +++ b/OvmfPkg/PlatformPei/Platform.c @@ -218,11 +218,10 @@ MemMapInitialization ( TopOfLowRam = GetSystemMemorySizeBelow4gb (); if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) { // - // A 3GB base will always fall into Q35's 32-bit PCI host aperture, - // regardless of the Q35 MMCONFIG BAR. Correspondingly, QEMU never lets - // the RAM below 4 GB exceed it. + // On Q35 machine types that QEMU intends to support in the long term, + // QEMU never lets the RAM below 4 GB exceed 2 GB. // - PciBase = BASE_2GB + BASE_1GB; + PciBase = BASE_2GB; ASSERT (TopOfLowRam <= PciBase); } else { PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;