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[198.145.21.10]) by mx.google.com with ESMTPS id s64si21663498pfk.75.2016.09.12.06.06.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 12 Sep 2016 06:06:13 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id C99A31A1E0B; Mon, 12 Sep 2016 06:06:12 -0700 (PDT) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received: from mail-wm0-x233.google.com (mail-wm0-x233.google.com [IPv6:2a00:1450:400c:c09::233]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 5F5571A1E0A for ; Mon, 12 Sep 2016 06:06:11 -0700 (PDT) Received: by mail-wm0-x233.google.com with SMTP id 1so143636418wmz.1 for ; Mon, 12 Sep 2016 06:06:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=RGWMjVni3VY652aceKG24ZFmTW/kmtKFHOuSQvmerIA=; b=GbXXkgPg+XjcfIn/s9huqeJu8RhmOoOukFfn8xvqi9OqWyLUhKlSg2EPgY4qWR6wx0 YqTEjwtaD+//xRPJAYqULm6VDQUbvew8rbUt0Ez2ACcRDqU/zu7CjWUlAXAcm2LKQWzb sUXkSP/zdrYQzaSPmi8jlq+BicnfYJYKEVaDE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=RGWMjVni3VY652aceKG24ZFmTW/kmtKFHOuSQvmerIA=; b=Un0q9kvNGd1GUQ2i4psRNc6AFkuLc6eVmmT7So/M7YWwFs7bifnFt/zUDeK682Uf+5 /nfGoKcy6Dv7+Gh42J6OZCYqkEFgEA/QgiWcyEY4JV5jTiOkt8+6OSD37bKw3khNUdhU cj0jEnsaW/EUPdO0isfu5p9/gsbrtiaNSbzWkBaYZTtqfPcDUiETQcNKWPp8ocKRjGyT myx0vhkQjrCDotOd2FVG7YyqBo5tBlKlPPsi5vVA0EEipNiDNhuGkgm9+4IoAsnALr4R NbVIwNkbjMC9n3Qplu3fz9cKSFBGgticAp7A7dX+ph3aKWhAMSZK6dYxc3Rp4nQbkSdI OeMQ== X-Gm-Message-State: AE9vXwPoX8bpiGnxgCkj1FxJwOeucyX15v54Yd9wsSIShYDgQzbaIOt7FtR23ungSKdPRMyT X-Received: by 10.194.118.39 with SMTP id kj7mr14247860wjb.172.1473685569773; Mon, 12 Sep 2016 06:06:09 -0700 (PDT) Received: from localhost.localdomain ([197.128.106.42]) by smtp.gmail.com with ESMTPSA id r194sm3658033wmf.22.2016.09.12.06.06.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 12 Sep 2016 06:06:08 -0700 (PDT) From: Ard Biesheuvel To: edk2-devel@lists.01.org, liming.gao@intel.com, star.zeng@intel.com, feng.tian@intel.com, ruiyu.ni@intel.com Date: Mon, 12 Sep 2016 14:06:01 +0100 Message-Id: <1473685561-1418-1-git-send-email-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.7.4 Subject: [edk2] [PATCH] MdeModulePkg/PciBusDxe: make BAR degradation dependent on OPROM presence X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lersek@redhat.com, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" The practice of unconditionally degrading 64-bit PCI MMIO BARs to 32-bit if the device in question happens to have an option ROM is based on platform constraints, not architectural constraints, and really only makes sense on Intel platforms that contain a CSM implementation. So let's copy the OVMF code that checks for the presence of the legacy BIOS protocol (&gEfiLegacyBiosProtocolGuid), and only perform the BAR degradation if this protocol is installed. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c | 42 ++++++++++ MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 1 + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 2 + MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c | 83 ++++++++++---------- 4 files changed, 88 insertions(+), 40 deletions(-) -- 2.7.4 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c index a463bea80f3d..857f3e11b6bd 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.c @@ -49,6 +49,39 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_PCI_HOTPLUG_REQUEST_PROTOCOL mPciHotPlugReques }; /** + Legacy BIOS installed callback + + @param[in] Event Event whose notification function is being invoked. + @param[in] Context Pointer to the notification function's context. + +**/ +STATIC +VOID +EFIAPI +LegacyBiosInstalledCallBack ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + EFI_STATUS Status; + EFI_LEGACY_BIOS_PROTOCOL *LegacyBios; + + Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid, + NULL /* Registration */, (VOID **)&LegacyBios); + if (EFI_ERROR (Status)) { + return; + } + + mLegacyBiosInstalled = TRUE; + + // + // Close the event and deregister this callback. + // + Status = gBS->CloseEvent (Event); + ASSERT_EFI_ERROR (Status); +} + +/** The Entry Point for PCI Bus module. The user code starts with this function. Installs driver module protocols and. Creates virtual device handles for ConIn, @@ -72,6 +105,7 @@ PciBusEntryPoint ( { EFI_STATUS Status; EFI_HANDLE Handle; + VOID *Registration; // // Initializes PCI devices pool @@ -91,6 +125,14 @@ PciBusEntryPoint ( ); ASSERT_EFI_ERROR (Status); + EfiCreateProtocolNotifyEvent ( + &gEfiLegacyBiosProtocolGuid, + TPL_CALLBACK, + LegacyBiosInstalledCallBack, + NULL, + &Registration + ); + if (FeaturePcdGet (PcdPciBusHotplugDeviceSupport)) { // // If Hot Plug is supported, install EFI PCI Hot Plug Request protocol. diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h index b12d7ec5032f..2bf5695476a1 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h @@ -321,6 +321,7 @@ extern EFI_PCI_PLATFORM_PROTOCOL *gPciPlatformProtocol; extern EFI_PCI_OVERRIDE_PROTOCOL *gPciOverrideProtocol; extern BOOLEAN mReserveIsaAliases; extern BOOLEAN mReserveVgaAliases; +extern BOOLEAN mLegacyBiosInstalled; /** Macro that checks whether device is a GFX device. diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf index 330ccc8cbffc..b843ccc49934 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf @@ -66,6 +66,7 @@ [Sources] [Packages] MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec + IntelFrameworkPkg/IntelFrameworkPkg.dec [LibraryClasses] PcdLib @@ -95,6 +96,7 @@ [Protocols] gEfiPciRootBridgeIoProtocolGuid ## TO_START gEfiIncompatiblePciDeviceSupportProtocolGuid ## SOMETIMES_CONSUMES gEfiLoadFile2ProtocolGuid ## SOMETIMES_PRODUCES + gEfiLegacyBiosProtocolGuid ## SOMETIMES_CONSUMES [FeaturePcd] gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport ## CONSUMES diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c index b0632d53b82b..6637625b210d 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c @@ -17,9 +17,10 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. // // The default policy for the PCI bus driver is NOT to reserve I/O ranges for both ISA aliases and VGA aliases. // -BOOLEAN mReserveIsaAliases = FALSE; -BOOLEAN mReserveVgaAliases = FALSE; -BOOLEAN mPolicyDetermined = FALSE; +BOOLEAN mReserveIsaAliases = FALSE; +BOOLEAN mReserveVgaAliases = FALSE; +BOOLEAN mPolicyDetermined = FALSE; +BOOLEAN mLegacyBiosInstalled = FALSE; /** The function is used to skip VGA range. @@ -1058,48 +1059,50 @@ DegradeResource ( LIST_ENTRY *NextChildNodeLink; PCI_RESOURCE_NODE *ResourceNode; - // - // If any child device has both option ROM and 64-bit BAR, degrade its PMEM64/MEM64 - // requests in case that if a legacy option ROM image can not access 64-bit resources. - // - ChildDeviceLink = Bridge->ChildList.ForwardLink; - while (ChildDeviceLink != NULL && ChildDeviceLink != &Bridge->ChildList) { - PciIoDevice = PCI_IO_DEVICE_FROM_LINK (ChildDeviceLink); - if (PciIoDevice->RomSize != 0) { - if (!IsListEmpty (&Mem64Node->ChildList)) { - ChildNodeLink = Mem64Node->ChildList.ForwardLink; - while (ChildNodeLink != &Mem64Node->ChildList) { - ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink); - NextChildNodeLink = ChildNodeLink->ForwardLink; - - if ((ResourceNode->PciDev == PciIoDevice) && - (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed) - ) { - RemoveEntryList (ChildNodeLink); - InsertResourceNode (Mem32Node, ResourceNode); + if (mLegacyBiosInstalled) { + // + // If any child device has both option ROM and 64-bit BAR, degrade its PMEM64/MEM64 + // requests in case that if a legacy option ROM image can not access 64-bit resources. + // + ChildDeviceLink = Bridge->ChildList.ForwardLink; + while (ChildDeviceLink != NULL && ChildDeviceLink != &Bridge->ChildList) { + PciIoDevice = PCI_IO_DEVICE_FROM_LINK (ChildDeviceLink); + if (PciIoDevice->RomSize != 0) { + if (!IsListEmpty (&Mem64Node->ChildList)) { + ChildNodeLink = Mem64Node->ChildList.ForwardLink; + while (ChildNodeLink != &Mem64Node->ChildList) { + ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink); + NextChildNodeLink = ChildNodeLink->ForwardLink; + + if ((ResourceNode->PciDev == PciIoDevice) && + (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed) + ) { + RemoveEntryList (ChildNodeLink); + InsertResourceNode (Mem32Node, ResourceNode); + } + ChildNodeLink = NextChildNodeLink; } - ChildNodeLink = NextChildNodeLink; - } - } + } - if (!IsListEmpty (&PMem64Node->ChildList)) { - ChildNodeLink = PMem64Node->ChildList.ForwardLink; - while (ChildNodeLink != &PMem64Node->ChildList) { - ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink); - NextChildNodeLink = ChildNodeLink->ForwardLink; - - if ((ResourceNode->PciDev == PciIoDevice) && - (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed) - ) { - RemoveEntryList (ChildNodeLink); - InsertResourceNode (PMem32Node, ResourceNode); + if (!IsListEmpty (&PMem64Node->ChildList)) { + ChildNodeLink = PMem64Node->ChildList.ForwardLink; + while (ChildNodeLink != &PMem64Node->ChildList) { + ResourceNode = RESOURCE_NODE_FROM_LINK (ChildNodeLink); + NextChildNodeLink = ChildNodeLink->ForwardLink; + + if ((ResourceNode->PciDev == PciIoDevice) && + (ResourceNode->Virtual || !PciIoDevice->PciBar[ResourceNode->Bar].BarTypeFixed) + ) { + RemoveEntryList (ChildNodeLink); + InsertResourceNode (PMem32Node, ResourceNode); + } + ChildNodeLink = NextChildNodeLink; } - ChildNodeLink = NextChildNodeLink; - } - } + } + } + ChildDeviceLink = ChildDeviceLink->ForwardLink; } - ChildDeviceLink = ChildDeviceLink->ForwardLink; } //