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[198.145.21.10]) by mx.google.com with ESMTPS id f17si9056949pga.566.2017.11.10.06.22.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:22:47 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=VJFu+66g; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 09B522035561B; Fri, 10 Nov 2017 06:18:22 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::242; helo=mail-wm0-x242.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 73D5821B00DE8 for ; Fri, 10 Nov 2017 06:18:21 -0800 (PST) Received: by mail-wm0-x242.google.com with SMTP id t139so3093400wmt.1 for ; Fri, 10 Nov 2017 06:22:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=IPr7AbXPPgixWsBE7QeQvFZqBjvEI/igEvxr7mqMwYs=; b=VJFu+66gg+jI9SqIkGLz9rL87Wgdf0PRZPwiy5rfdAtXrKhnXKZFJQBqfPYrdDBBPw 8PYBeyI3LmcDEcQyw4ZS9/Ww1oUUCAsoyD2u9lOynLluWRMH6KJHn6GtxRO1SSURkUqB 5yvg9QOaTka/7Ns4js4k2tS0p4BQSvpKD12QY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=IPr7AbXPPgixWsBE7QeQvFZqBjvEI/igEvxr7mqMwYs=; b=BbapwXR8NkSpczOdxpyr1bdpyUFRms8Usq/DMUX0wNekxljyCOadli/13+eGOt5r+r X3hRI4kYksju3lAHcn2aodkVwVV7FtS1FHDEdoha7XPKEXHK/hiNHs03H3X45Kv2Qoy4 21beweBVCKIAcc/SyEyeM+J09MkXLX9OKmX0FhNhnuNHxSy73/4vxmQhIjvTGMkp8cBX iRtiS29klc2bQSPW/lwPWm5lwqvV94hW5jWXgv0ldaDZsxSoWH5uYAK0RqeHI+lSM2x5 rmHuxq8lhAMNXA/gxW0ZuKM6gm6kGeKV40/qvJTX+1gyEuYHJAhc8jpWU1cuay+LeoL7 TR2Q== X-Gm-Message-State: AJaThX6cLVhhvhPzX/GV8f3WaAgvyMhRChFsQXJlt5iJcAOZaFEl7I2d MJE8LwTbvwYD/QRaYYi7RVeHM135RaI= X-Received: by 10.28.32.136 with SMTP id g130mr398686wmg.102.1510323742836; Fri, 10 Nov 2017 06:22:22 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id e131sm1036477wmg.15.2017.11.10.06.22.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:22:22 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Date: Fri, 10 Nov 2017 14:21:06 +0000 Message-Id: <20171110142127.12018-14-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171110142127.12018-1-ard.biesheuvel@linaro.org> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 13/34] Silicon/SynQuacer: add NorFlashPlatformLib implementation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Add the platform glue for the NOR flash driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c | 70 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf | 41 ++++++++++++ 2 files changed, 111 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c new file mode 100644 index 000000000000..816d8ba33f8c --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacer.c @@ -0,0 +1,70 @@ +/** @file + + Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+ + This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + **/ + +#include +#include +#include +#include + +#include + +STATIC NOR_FLASH_DESCRIPTION mNorFlashDevices[] = { + { + // UEFI code region + SYNQUACER_SPI_NOR_BASE, // device base + FixedPcdGet64 (PcdFdBaseAddress), // region base + FixedPcdGet32 (PcdFdSize), // region size + SIZE_64KB, // block size + { + 0x19c118b0, 0xc423, 0x42be, { 0xb8, 0x0f, 0x70, 0x6f, 0x1f, 0xcb, 0x59, 0x9a } + } + }, + { + // Environment variable region + SYNQUACER_SPI_NOR_BASE, // device base + FixedPcdGet32 (PcdFlashNvStorageVariableBase), // region base + FixedPcdGet32 (PcdFlashNvStorageVariableSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) + + FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize), // region size + SIZE_64KB, // block size + { + 0x3105bd7a, 0x82c3, 0x486f, { 0xb1, 0x03, 0x1e, 0x09, 0x54, 0xec, 0x85, 0x75 } + } + }, +}; + +EFI_STATUS +NorFlashPlatformInitialization ( + VOID + ) +{ + return EFI_SUCCESS; +} + +EFI_STATUS +NorFlashPlatformGetDevices ( + OUT NOR_FLASH_DESCRIPTION **NorFlashDevices, + OUT UINT32 *Count + ) +{ + if (NorFlashDevices == NULL || + Count == NULL) { + return EFI_INVALID_PARAMETER; + } + + *Count = ARRAY_SIZE (mNorFlashDevices); + *NorFlashDevices = mNorFlashDevices; + + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf new file mode 100644 index 000000000000..2a8fd209f5e3 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/NorFlashSynQuacerLib/NorFlashSynQuacerLib.inf @@ -0,0 +1,41 @@ +#/** @file +# +# Copyright (c) 2011 - 2014, ARM Ltd. All rights reserved.
+# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = NorFlashSynQuacerLib + FILE_GUID = 8279227C-C555-4D75-B439-D8A959635CDD + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = NorFlashPlatformLib + +[Sources] + NorFlashSynQuacer.c + +[Packages] + ArmPlatformPkg/ArmPlatformPkg.dec + ArmPkg/ArmPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[LibraryClasses] + BaseLib + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize