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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id d24si6999310pls.749.2017.11.10.06.22.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:22:14 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=eNg0HiYm; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 167CC20355233; Fri, 10 Nov 2017 06:18:02 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id AC58121B00DD1 for ; Fri, 10 Nov 2017 06:18:00 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id p96so8730408wrb.7 for ; Fri, 10 Nov 2017 06:22:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=U67r50UwZSV/fEsjjvwoEwhQu1TSMUrN2gYfR6y8SOg=; b=eNg0HiYmE7LPeBG+mBhlLNfTkHb7iG7fC/6f2mrV4wdm9ENTVtyjcoNsxb/uX6DjZg LkmbtgxgJg2NuGlWY/tM33oAti6wf21tDJDj0z8AoWy7ZYuFltg/3r2hO1FGFFbKeQYF h5nlHPKlXkIJCEGn9w/sfd4yfMsNB4Q3FmpS0= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=U67r50UwZSV/fEsjjvwoEwhQu1TSMUrN2gYfR6y8SOg=; b=kWTyKyOEcGGL7CZF51wqyXTPqf6sGapeIAPtTwTv7oMxSklvtz9gV4GwqZ163CbZ4G fMd8HrpAZz0dCbINn6HTril4fgN1fVG4NOCbGwPPTY6Zn49eIl29h1X1gRL0f4WVfu4Q Nrj3ci48TtnnZedjBssuVGwt12BGc0v+L+ImTBln6JOqASiN6Pcp1u+JE+OBFdw/4i+l YbCYq8788J7TdbASbvysqwAOLzuCH1iduyGiSd1c76cikxs+z1SR8RGwAzlyzBbhlGzh 05YTpEyBW3bTGkJGBp9IH93mrRiTVXLDSF9QrqujOAS64ReA4Av/9VB4ExxXg2s6xAEs y4iA== X-Gm-Message-State: AJaThX7ColhOmACGR2cm8laGmfRGfEe+mEh3nR5d4KsCEHfcWxl4tTju 7f4kooJISeQY+zSTFPo4iOwf8a24kU0= X-Received: by 10.223.179.194 with SMTP id x2mr486025wrd.266.1510323721998; Fri, 10 Nov 2017 06:22:01 -0800 (PST) Received: from localhost.localdomain ([160.167.170.128]) by smtp.gmail.com with ESMTPSA id e131sm1036477wmg.15.2017.11.10.06.21.59 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 10 Nov 2017 06:22:01 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org, leif.lindholm@linaro.org, daniel.thompson@linaro.org Date: Fri, 10 Nov 2017 14:20:58 +0000 Message-Id: <20171110142127.12018-6-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171110142127.12018-1-ard.biesheuvel@linaro.org> References: <20171110142127.12018-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms v4 05/34] Silicon/SynQuacer: add MemoryInitPeiLib implementation X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: masahisa.kojima@linaro.org, masami.hiramatsu@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" Implement MemoryInitPeiLib based on the newly added DramInfo PPI, which retrieves the DRAM information from lower level firmware. Note that the firmware volumes in SPI NOR are mapped with different attributes: the FV containing the PEI modules that may execute in place is mapped as uncached memory, given that it requires executable permissions. The FV containing the compressed DXE modules is mapped with device attributes for performance (!), and copied into DRAM by the platform PEIM once permanent memory is installed. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm --- v4: use non-shareable writeback cacheable memory type for SPI NOR and EEPROM add GPIO block Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c | 186 ++++++++++++++++++++ Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf | 65 +++++++ 2 files changed, 251 insertions(+) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c new file mode 100644 index 000000000000..30b42080d515 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.c @@ -0,0 +1,186 @@ +/** @file +* +* Copyright (c) 2011-2015, ARM Limited. All rights reserved. +* Copyright (c) 2017, Linaro, Ltd. All rights reserved. +* +* This program and the accompanying materials +* are licensed and made available under the terms and conditions of the BSD License +* which accompanies this distribution. The full text of the license may be found at +* http://opensource.org/licenses/bsd-license.php +* +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +* +**/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#define ARM_MEMORY_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK } + +#define ARM_UNCACHED_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED } + +#define ARM_DEVICE_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_DEVICE } + +#define ARM_CACHED_DEVICE_REGION(Base, Size) \ + { (Base), (Base), (Size), ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK_NONSHAREABLE } + +VOID +BuildMemoryTypeInformationHob ( + VOID + ); + +STATIC CONST EFI_RESOURCE_ATTRIBUTE_TYPE mDramResourceAttributes = + EFI_RESOURCE_ATTRIBUTE_PRESENT | + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | + EFI_RESOURCE_ATTRIBUTE_TESTED; + +STATIC CONST ARM_MEMORY_REGION_DESCRIPTOR mVirtualMemoryTable[] = { + // Memory mapped SPI NOR flash + ARM_CACHED_DEVICE_REGION (FixedPcdGet64 (PcdFdBaseAddress), + FixedPcdGet32 (PcdFdSize)), + + // SynQuacer OnChip peripherals + ARM_DEVICE_REGION (SYNQUACER_PERIPHERALS_BASE, + SYNQUACER_PERIPHERALS_SZ), + + // SynQuacer OnChip non-secure SRAM + ARM_CACHED_DEVICE_REGION (SYNQUACER_NON_SECURE_SRAM_BASE, + SYNQUACER_NON_SECURE_SRAM_SZ), + + // SynQuacer GIC-500 + ARM_DEVICE_REGION (SYNQUACER_GIC500_DIST_BASE, SYNQUACER_GIC500_DIST_SIZE), + ARM_DEVICE_REGION (SYNQUACER_GIC500_RDIST_BASE, SYNQUACER_GIC500_RDIST_SIZE), + + // SynQuacer eMMC(SDH30) + ARM_DEVICE_REGION (SYNQUACER_EMMC_BASE, SYNQUACER_EMMC_BASE_SZ), + + // SynQuacer GPIO block + ARM_DEVICE_REGION (SYNQUACER_GPIO_BASE, SYNQUACER_GPIO_SIZE), + + // SynQuacer EEPROM - could point to NOR flash as well + ARM_CACHED_DEVICE_REGION (FixedPcdGet32 (PcdNetsecEepromBase), + SYNQUACER_EEPROM_BASE_SZ), + + // SynQuacer NETSEC + ARM_DEVICE_REGION (SYNQUACER_NETSEC1_BASE, SYNQUACER_NETSEC1_BASE_SZ), + + // PCIe control registers + ARM_DEVICE_REGION (SYNQUACER_PCIE_BASE, SYNQUACER_PCIE_SIZE), + + // PCIe config space + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_CONFIG_BASE, + SYNQUACER_PCI_SEG0_CONFIG_SIZE), + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_CONFIG_BASE, + SYNQUACER_PCI_SEG1_CONFIG_SIZE), + + // PCIe I/O space + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG0_PORTIO_MEMBASE, + SYNQUACER_PCI_SEG0_PORTIO_MEMSIZE), + ARM_DEVICE_REGION (SYNQUACER_PCI_SEG1_PORTIO_MEMBASE, + SYNQUACER_PCI_SEG1_PORTIO_MEMSIZE), +}; + +STATIC +EFI_STATUS +DeclareDram ( + OUT ARM_MEMORY_REGION_DESCRIPTOR **VirtualMemoryTable + ) +{ + SYNQUACER_DRAM_INFO_PPI *DramInfo; + EFI_STATUS Status; + UINTN Idx; + UINTN RegionCount; + UINT64 Base; + UINT64 Size; + ARM_MEMORY_REGION_DESCRIPTOR *DramDescriptor; + + Status = PeiServicesLocatePpi (&gSynQuacerDramInfoPpiGuid, 0, NULL, + (VOID **)&DramInfo); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = DramInfo->GetRegionCount (&RegionCount); + if (EFI_ERROR (Status)) { + return Status; + } + + *VirtualMemoryTable = AllocatePool (sizeof (mVirtualMemoryTable) + + (RegionCount + 1) * + sizeof (ARM_MEMORY_REGION_DESCRIPTOR)); + if (*VirtualMemoryTable == NULL) { + return EFI_OUT_OF_RESOURCES; + } + CopyMem (*VirtualMemoryTable, mVirtualMemoryTable, + sizeof (mVirtualMemoryTable)); + + DramDescriptor = *VirtualMemoryTable + ARRAY_SIZE (mVirtualMemoryTable); + + for (Idx = 0; Idx < RegionCount; Idx++, DramDescriptor++) { + Status = DramInfo->GetRegion (Idx, &Base, &Size); + ASSERT_EFI_ERROR (Status); + + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, + mDramResourceAttributes, Base, Size); + + DramDescriptor->PhysicalBase = Base; + DramDescriptor->VirtualBase = Base; + DramDescriptor->Length = Size; + DramDescriptor->Attributes = ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK; + } + + DramDescriptor->PhysicalBase = 0; + DramDescriptor->VirtualBase = 0; + DramDescriptor->Length = 0; + DramDescriptor->Attributes = 0; + + return EFI_SUCCESS; +} + +EFI_STATUS +EFIAPI +MemoryPeim ( + IN EFI_PHYSICAL_ADDRESS UefiMemoryBase, + IN UINT64 UefiMemorySize + ) +{ + EFI_STATUS Status; + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; + + Status = DeclareDram (&VirtualMemoryTable); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + Status = ArmConfigureMmu (VirtualMemoryTable, NULL, NULL); + ASSERT_EFI_ERROR (Status); + if (EFI_ERROR (Status)) { + return Status; + } + + if (FeaturePcdGet (PcdPrePiProduceMemoryTypeInformationHob)) { + // Optional feature that helps prevent EFI memory map fragmentation. + BuildMemoryTypeInformationHob (); + } + return EFI_SUCCESS; +} diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf new file mode 100644 index 000000000000..161072a33d99 --- /dev/null +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerMemoryInitPeiLib/SynQuacerMemoryInitPeiLib.inf @@ -0,0 +1,65 @@ +#/** @file +# +# Copyright (c) 2011-2014, ARM Ltd. All rights reserved.
+# Copyright (c) 2017, Linaro, Ltd. All rights reserved.
+# +# This program and the accompanying materials +# are licensed and made available under the terms and conditions of the BSD License +# which accompanies this distribution. The full text of the license may be found at +# http://opensource.org/licenses/bsd-license.php +# +# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +# +#**/ + +[Defines] + INF_VERSION = 0x00010019 + BASE_NAME = SynQuacerMemoryInitPeiLib + FILE_GUID = c69d3ce7-098c-4fcd-afb4-15fb05a39308 + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = MemoryInitPeiLib|SEC PEIM + +[Sources] + SynQuacerMemoryInitPeiLib.c + +[Packages] + ArmPkg/ArmPkg.dec + EmbeddedPkg/EmbeddedPkg.dec + MdeModulePkg/MdeModulePkg.dec + MdePkg/MdePkg.dec + Silicon/Socionext/SynQuacer/SynQuacer.dec + +[LibraryClasses] + ArmLib + ArmMmuLib + BaseMemoryLib + DebugLib + MemoryAllocationLib + PeiServicesLib + +[FeaturePcd] + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob + +[FixedPcd] + gArmTokenSpaceGuid.PcdFdBaseAddress + gArmTokenSpaceGuid.PcdFdSize + gArmTokenSpaceGuid.PcdGicDistributorBase + gArmTokenSpaceGuid.PcdGicRedistributorsBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize + gSynQuacerTokenSpaceGuid.PcdNetsecEepromBase + +[Pcd] + gArmTokenSpaceGuid.PcdSystemMemoryBase + +[Ppis] + gSynQuacerDramInfoPpiGuid ## CONSUMES + +[Depex] + gSynQuacerDramInfoPpiGuid