[edk2,v2,09/13] ArmPlatformPkg: remove unused PL35x driver

diff --git a/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.S b/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.S
deleted file mode 100644
index a26a4d43770e..000000000000
--- a/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.S
+++ /dev/null
@@ -1,60 +0,0 @@ 
-#
-#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#
-
-#include <AsmMacroIoLib.h>
-#include <Library/PcdLib.h>
-#include <AutoGen.h>
-#include <Drivers/PL35xSmc.h>
-
-.text
-
-#Maintain 8 byte alignment
-.align 3
-
-GCC_ASM_EXPORT(PL35xSmcInitialize)
-GCC_ASM_EXPORT(PL35xSmcSetRefresh)
-
-// IN r1 Smc Base Address
-// IN r2 Smc Configuration Start Address
-// IN r3 Smc Configuration End Address
-// NOTE: This code is been called before any stack has been setup. It means some registers
-//       could be overwritten (case of 'r0')
-ASM_PFX(PL35xSmcInitialize):
-  // While (SmcConfigurationStart < SmcConfigurationEnd)
-  cmp   r2, r3
-  blxge lr
-
-  // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
-  ldr   r0, [r2, #0x4]
-  str   r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]
-
-  // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
-  ldr   r0, [r2, #0x8]
-  str   r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]
-
-  // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
-  ldr   r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
-  ldr   r4, [r2, #0x0]
-  orr   r0, r0, r4
-  str   r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]
-
-  add   r2, #0xC
-  b     ASM_PFX(PL35xSmcInitialize)
-
-// IN r1 Smc Base Address
-// IN r2 Smc Refresh Period 0
-// IN r3 Smc Refresh Period 1
-ASM_PFX(PL35xSmcSetRefresh):
-  str   r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]
-  str   r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]
-  blx lr
diff --git a/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.asm b/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.asm
deleted file mode 100644
index 661b0688c85c..000000000000
--- a/ArmPlatformPkg/Drivers/PL35xSmc/InitializeSMC.asm
+++ /dev/null
@@ -1,62 +0,0 @@ 
-//
-//  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-//
-//  This program and the accompanying materials
-//  are licensed and made available under the terms and conditions of the BSD License
-//  which accompanies this distribution.  The full text of the license may be found at
-//  http://opensource.org/licenses/bsd-license.php
-//
-//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-//
-//
-
-#include <AsmMacroIoLib.h>
-#include <Library/PcdLib.h>
-#include <Drivers/PL35xSmc.h>
-#include <AutoGen.h>
-
-  INCLUDE AsmMacroIoLib.inc
-
-  EXPORT  PL35xSmcInitialize
-  EXPORT  PL35xSmcSetRefresh
-
-  PRESERVE8
-  AREA    ModuleInitializeSMC, CODE, READONLY
-
-// IN r1 Smc Base Address
-// IN r2 Smc Configuration Start Address
-// IN r3 Smc Configuration End Address
-// NOTE: This code is been called before any stack has been setup. It means some registers
-//       could be overwritten (case of 'r0')
-PL35xSmcInitialize
-  // While (SmcConfigurationStart < SmcConfigurationEnd)
-  cmp   r2, r3
-  blxge lr
-
-  // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)
-  ldr   r0, [r2, #0x4]
-  str   r0, [r1, #PL350_SMC_SET_CYCLES_OFFSET]
-
-  // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)
-  ldr   r0, [r2, #0x8]
-  str   r0, [r1, #PL350_SMC_SET_OPMODE_OFFSET]
-
-  // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers
-  ldr   r0, =PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE
-  ldr   r4, [r2, #0x0]
-  orr   r0, r0, r4
-  str   r0, [r1, #PL350_SMC_DIRECT_CMD_OFFSET]
-
-  add   r2, #0xC
-  b     PL35xSmcInitialize
-
-// IN r1 Smc Base Address
-// IN r2 Smc Refresh Period 0
-// IN r3 Smc Refresh Period 1
-PL35xSmcSetRefresh
-  str   r2, [r1, #PL350_SMC_REFRESH_0_OFFSET]
-  str   r3, [r1, #PL350_SMC_REFRESH_1_OFFSET]
-  blx lr
-
-  END
diff --git a/ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf b/ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf
deleted file mode 100644
index 2eee5ab5056f..000000000000
--- a/ArmPlatformPkg/Drivers/PL35xSmc/PL35xSmc.inf
+++ /dev/null
@@ -1,29 +0,0 @@ 
-#/* @file
-#  Copyright (c) 2011, ARM Limited. All rights reserved.
-#
-#  This program and the accompanying materials
-#  are licensed and made available under the terms and conditions of the BSD License
-#  which accompanies this distribution.  The full text of the license may be found at
-#  http://opensource.org/licenses/bsd-license.php
-#
-#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-#
-#*/
-
-[Defines]
-  INF_VERSION                    = 0x00010005
-  BASE_NAME                      = PL35xSmc
-  FILE_GUID                      = 10952220-aa32-11df-a438-0002a5d5c51b
-  MODULE_TYPE                    = SEC
-  VERSION_STRING                 = 1.0
-  LIBRARY_CLASS                  = PL35xSmcLib
-
-[Sources.common]
-  InitializeSMC.asm  | RVCT
-  InitializeSMC.S    | GCC
-
-[Packages]
-  ArmPkg/ArmPkg.dec
-  ArmPlatformPkg/ArmPlatformPkg.dec
-  MdePkg/MdePkg.dec
diff --git a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h b/ArmPlatformPkg/Include/Drivers/PL35xSmc.h
deleted file mode 100644
index 750f5088b6de..000000000000
--- a/ArmPlatformPkg/Include/Drivers/PL35xSmc.h
+++ /dev/null
@@ -1,75 +0,0 @@ 
-/** @file
-*
-*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
-*
-*  This program and the accompanying materials
-*  are licensed and made available under the terms and conditions of the BSD License
-*  which accompanies this distribution.  The full text of the license may be found at
-*  http://opensource.org/licenses/bsd-license.php
-*
-*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
-*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
-*
-**/
-
-#ifndef PL35xSMC_H_
-#define PL35xSMC_H_
-
-#define PL350_SMC_DIRECT_CMD_OFFSET   0x10
-#define PL350_SMC_SET_CYCLES_OFFSET   0x14
-#define PL350_SMC_SET_OPMODE_OFFSET   0x18
-#define PL350_SMC_REFRESH_0_OFFSET    0x20
-#define PL350_SMC_REFRESH_1_OFFSET    0x24
-
-#define PL350_SMC_DIRECT_CMD_ADDR(addr)                 ((addr) & 0xFFFFF)
-#define PL350_SMC_DIRECT_CMD_ADDR_SET_CRE               (1 << 20)
-#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE_UPDATE       (3 << 21)
-#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE            (2 << 21)
-#define PL350_SMC_DIRECT_CMD_ADDR_CMD_MODE              (1 << 21)
-#define PL350_SMC_DIRECT_CMD_ADDR_CMD_UPDATE_AXI        (0 << 21)
-#define PL350_SMC_DIRECT_CMD_ADDR_CS_INTERF(interf,chip) (((interf) << 25) | ((chip) << 23))
-#define PL350_SMC_DIRECT_CMD_ADDR_CS(ChipSelect)        (((ChipSelect) & 0x7) << 23)
-
-#define PL350_SMC_SET_OPMODE_MEM_WIDTH_8                (0 << 0)
-#define PL350_SMC_SET_OPMODE_MEM_WIDTH_16               (1 << 0)
-#define PL350_SMC_SET_OPMODE_MEM_WIDTH_32               (2 << 0)
-#define PL350_SMC_SET_OPMODE_SET_RD_SYNC                (1 << 2)
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_1      (0 << 3)
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_4      (1 << 3)
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_8      (2 << 3)
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_16     (3 << 3)
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_32     (4 << 3)
-#define PL350_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT   (5 << 3)
-#define PL350_SMC_SET_OPMODE_SET_WR_SYNC                (1 << 6)
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_1      (0 << 7)
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_4      (1 << 7)
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_8      (2 << 7)
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_16     (3 << 7)
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_32     (4 << 7)
-#define PL350_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT   (5 << 7)
-#define PL350_SMC_SET_OPMODE_SET_BAA                    (1 << 10)
-#define PL350_SMC_SET_OPMODE_SET_ADV                    (1 << 11)
-#define PL350_SMC_SET_OPMODE_SET_BLS                    (1 << 12)
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_ANY        (0 << 13)
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_32         (1 << 13)
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_64         (2 << 13)
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_128        (3 << 13)
-#define PL350_SMC_SET_OPMODE_SET_BURST_ALIGN_256        (4 << 13)
-
-#define PL350_SMC_SET_CYCLE_NAND_T_RC(t)                (((t) & 0xF) << 0)
-#define PL350_SMC_SET_CYCLE_NAND_T_WC(t)                (((t) & 0xF) << 4)
-#define PL350_SMC_SET_CYCLE_NAND_T_REA(t)              (((t) & 0x7) << 8)
-#define PL350_SMC_SET_CYCLE_NAND_T_WP(t)                (((t) & 0x7) << 11)
-#define PL350_SMC_SET_CYCLE_NAND_T_CLR(t)                (((t) & 0x7) << 14)
-#define PL350_SMC_SET_CYCLE_NAND_T_AR(t)                (((t) & 0x7) << 17)
-#define PL350_SMC_SET_CYCLE_NAND_T_RR(t)                (((t) & 0x7) << 20)
-
-#define PL350_SMC_SET_CYCLE_SRAM_T_RC(t)                (((t) & 0xF) << 0)
-#define PL350_SMC_SET_CYCLE_SRAM_T_WC(t)                (((t) & 0xF) << 4)
-#define PL350_SMC_SET_CYCLE_SRAM_T_CEOE(t)              (((t) & 0x7) << 8)
-#define PL350_SMC_SET_CYCLE_SRAM_T_WP(t)                (((t) & 0x7) << 11)
-#define PL350_SMC_SET_CYCLE_SRAM_T_PC(t)                (((t) & 0x7) << 14)
-#define PL350_SMC_SET_CYCLE_SRAM_T_TR(t)                (((t) & 0x7) << 17)
-#define PL350_SMC_SET_CYCLE_SRAM_WE_TIME                (1 << 20)
-
-#endif