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[198.145.21.10]) by mx.google.com with ESMTPS id n12si10060789pgr.71.2017.12.04.14.23.33 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Dec 2017 14:23:33 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) client-ip=198.145.21.10; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=OUe/AUKA; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 198.145.21.10 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 2094820356247; Mon, 4 Dec 2017 14:18:51 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c09::241; helo=mail-wm0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id A52ED20356241 for ; Mon, 4 Dec 2017 14:18:49 -0800 (PST) Received: by mail-wm0-x241.google.com with SMTP id b76so17137225wmg.1 for ; Mon, 04 Dec 2017 14:23:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=NpQFWCRe7WmBC4VkTcuq7Lv7ivhtkVMq/2AaOk8CRD8=; b=OUe/AUKAg98ugbhCgxfyYkAVgq5y3x8lCEMJHMTpHlgHFCx2KjpTXyVZMXSs4VtVv8 aC9EIZ23W6QwLwkqzqtBb1i2hEn6ST/C9iTvWy656rexmKgT9yyPz05EMLO1fXrjgXQc 0eOqWWBGFFTSKBjp/9OjPN1PodEtKoS3sA32U= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=NpQFWCRe7WmBC4VkTcuq7Lv7ivhtkVMq/2AaOk8CRD8=; b=mMQ3leOdChQph6AvvX+Qec/7lIs/MHkugSFAjU3s+8MfFWHJ+DosZNKltJo4Lyh4vu 0BO0mAM5lN3tlwkPbGvNCJ5x+MRZuKirlJG1i+597eeL/lBLTFPvNE+TDUAk/DKfzGGK 1vJAF0yRC64KzcFBOv1jUrXKdlBfV1RGby7ARa6AxbuK6x9+mRj6RB2/0r8ZdXCBg+53 UB0r41xP8qf7Wx5bMrtVbB7hZbRnrAjsCJQMeULLaOvVmu9tdp9F0sTenxK8+7OzJNMz ppgADhulDmD4+1si1nEh2y+WLx56T1b5nUuq38x6TZyuJ3oKCeyxCG0I0GyGkp/us16k iedQ== X-Gm-Message-State: AKGB3mKXtvAYF+qox31X/cnwaKUjdgUEQRhedW0nLcVY4+hSJUdSwVsl lVwllauSIyErQo9O38GcLMi8eET2iKw= X-Received: by 10.28.92.146 with SMTP id q140mr4665792wmb.41.1512426198195; Mon, 04 Dec 2017 14:23:18 -0800 (PST) Received: from localhost.localdomain ([105.150.171.234]) by smtp.gmail.com with ESMTPSA id x133sm5667961wmd.44.2017.12.04.14.23.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 04 Dec 2017 14:23:17 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Mon, 4 Dec 2017 22:22:41 +0000 Message-Id: <20171204222243.15950-12-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171204222243.15950-1-ard.biesheuvel@linaro.org> References: <20171204222243.15950-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH v2 11/13] ArmPlatformPkg: remove unused PL310 driver X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" This driver is not used by any platforms so remove it. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel Reviewed-by-if-no-comments-by-15-Dec: Leif Lindholm --- ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2Cache.c | 126 -------------------- ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf | 31 ----- ArmPlatformPkg/Include/Drivers/PL310L2Cache.h | 79 ------------ 3 files changed, 236 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2Cache.c b/ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2Cache.c deleted file mode 100644 index 1a6ab33720e5..000000000000 --- a/ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2Cache.c +++ /dev/null @@ -1,126 +0,0 @@ -/** @file -* -* Copyright (c) 2011, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#include -#include -#include -#include -#include - -#define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val) -#define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg) - -// Initialize PL320 L2 Cache Controller -VOID -L2x0CacheInit ( - IN UINTN L2x0Base, - IN UINT32 L2x0TagLatencies, - IN UINT32 L2x0DataLatencies, - IN UINT32 L2x0AuxValue, - IN UINT32 L2x0AuxMask, - IN BOOLEAN CacheEnabled - ) -{ - UINT32 Data; - UINT32 Revision; - UINT32 Aux; - UINT32 PfCtl; - UINT32 PwrCtl; - - // Check if L2x0 is present and is an ARM implementation - Data = L2x0ReadReg(L2X0_CACHEID); - if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) { - ASSERT(0); - return; - } - - // Check if L2x0 is PL310 - if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) { - ASSERT(0); - return; - } - - // RTL release - Revision = Data & 0x3F; - - // Check if L2x0 is already enabled then we disable it - Data = L2x0ReadReg(L2X0_CTRL); - if (Data & L2X0_CTRL_ENABLED) { - L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED); - } - - // - // Set up global configurations - // - - // Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO - Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO; - // Use AWCACHE attributes for WA - Aux |= L2x0_AUXCTRL_AW_AWCACHE; - // Use default Size - Data = L2x0ReadReg(L2X0_AUXCTRL); - Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK; - // Use default associativity - Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY; - // Enabled I & D Prefetch - Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH; - - if (Revision >= 5) { - // Prefetch Offset Register - PfCtl = L2x0ReadReg(L2X0_PFCTRL); - // - Prefetch increment set to 0 - // - Prefetch dropping off - // - Double linefills off - L2x0WriteReg(L2X0_PFCTRL, PfCtl); - - // Power Control Register - L2X0_PWRCTRL - PwrCtl = L2x0ReadReg(L2X0_PWRCTRL); - // - Standby when idle off - // - Dynamic clock gating off - // - Nc,NC-shared dropping off - L2x0WriteReg(L2X0_PWRCTRL, PwrCtl); - } - - if (Revision >= 2) { - L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies); - L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies); - } else { - // PL310 old style latency is not supported yet - ASSERT(0); - } - - // Set the platform specific values - Aux = (Aux & L2x0AuxMask) | L2x0AuxValue; - - // Write Auxiliary value - L2x0WriteReg(L2X0_AUXCTRL, Aux); - - // - // Invalidate all entries in cache - // - L2x0WriteReg(L2X0_INVWAY, 0xffff); - // Poll cache maintenance register until invalidate operation is complete - while(L2x0ReadReg(L2X0_INVWAY) & 0xffff); - - // Write to the Lockdown D and Lockdown I Register 9 if required - // - Not required - - // Clear any residual raw interrupts - L2x0WriteReg(L2X0_INTCLEAR, 0x1FF); - - // Enable the cache - if (CacheEnabled) { - L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED); - } -} diff --git a/ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf b/ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf deleted file mode 100644 index 78f952a1d0c8..000000000000 --- a/ArmPlatformPkg/Drivers/PL310L2Cache/PL310L2CacheSec.inf +++ /dev/null @@ -1,31 +0,0 @@ -#/* @file -# Copyright (c) 2011, ARM Limited. All rights reserved. -# -# This program and the accompanying materials -# are licensed and made available under the terms and conditions of the BSD License -# which accompanies this distribution. The full text of the license may be found at -# http://opensource.org/licenses/bsd-license.php -# -# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -# -#*/ - -[Defines] - INF_VERSION = 0x00010005 - BASE_NAME = PL310L2Cache - FILE_GUID = 16ad4fe0-b5b1-11df-8cbf-0002a5d5c51b - MODULE_TYPE = SEC - VERSION_STRING = 1.0 - LIBRARY_CLASS = L2X0CacheLib - -[Sources] - PL310L2Cache.c - -[Packages] - ArmPkg/ArmPkg.dec - ArmPlatformPkg/ArmPlatformPkg.dec - MdePkg/MdePkg.dec - -[FixedPcd] - gArmTokenSpaceGuid.PcdL2x0ControllerBase diff --git a/ArmPlatformPkg/Include/Drivers/PL310L2Cache.h b/ArmPlatformPkg/Include/Drivers/PL310L2Cache.h deleted file mode 100644 index a61099806269..000000000000 --- a/ArmPlatformPkg/Include/Drivers/PL310L2Cache.h +++ /dev/null @@ -1,79 +0,0 @@ -/** @file -* -* Copyright (c) 2011, ARM Limited. All rights reserved. -* -* This program and the accompanying materials -* are licensed and made available under the terms and conditions of the BSD License -* which accompanies this distribution. The full text of the license may be found at -* http://opensource.org/licenses/bsd-license.php -* -* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. -* -**/ - -#ifndef L2CACHELIB_H_ -#define L2CACHELIB_H_ - -#define L2X0_CACHEID 0x000 -#define L2X0_CTRL 0x100 -#define L2X0_AUXCTRL 0x104 -#define L230_TAG_LATENCY 0x108 -#define L230_DATA_LATENCY 0x10C -#define L2X0_INTCLEAR 0x220 -#define L2X0_CACHE_SYNC 0x730 -#define L2X0_INVWAY 0x77C -#define L2X0_CLEAN_WAY 0x7BC -#define L2X0_PFCTRL 0xF60 -#define L2X0_PWRCTRL 0xF80 - -#define L2X0_CACHEID_IMPLEMENTER_ARM 0x41 -#define L2X0_CACHEID_PARTNUM_PL310 0x03 - -#define L2X0_CTRL_ENABLED 0x1 -#define L2X0_CTRL_DISABLED 0x0 - -#define L2X0_AUXCTRL_EXCLUSIVE (1 << 12) -#define L2X0_AUXCTRL_ASSOCIATIVITY (1 << 16) -#define L2X0_AUXCTRL_WAYSIZE_MASK (3 << 17) -#define L2X0_AUXCTRL_WAYSIZE_16KB (1 << 17) -#define L2X0_AUXCTRL_WAYSIZE_32KB (2 << 17) -#define L2X0_AUXCTRL_WAYSIZE_64KB (3 << 17) -#define L2X0_AUXCTRL_WAYSIZE_128KB (4 << 17) -#define L2X0_AUXCTRL_WAYSIZE_256KB (5 << 17) -#define L2X0_AUXCTRL_WAYSIZE_512KB (6 << 17) -#define L2X0_AUXCTRL_EM (1 << 20) -#define L2X0_AUXCTRL_SHARED_OVERRIDE (1 << 22) -#define L2x0_AUXCTRL_AW_AWCACHE (0 << 23) -#define L2x0_AUXCTRL_AW_NOALLOC (1 << 23) -#define L2x0_AUXCTRL_AW_OVERRIDE (2 << 23) -#define L2X0_AUXCTRL_SBO (1 << 25) -#define L2X0_AUXCTRL_NSAC (1 << 27) -#define L2x0_AUXCTRL_DPREFETCH (1 << 28) -#define L2x0_AUXCTRL_IPREFETCH (1 << 29) -#define L2x0_AUXCTRL_EARLY_BRESP (1 << 30) - -#define L2x0_LATENCY_1_CYCLE 0 -#define L2x0_LATENCY_2_CYCLES 1 -#define L2x0_LATENCY_3_CYCLES 2 -#define L2x0_LATENCY_4_CYCLES 3 -#define L2x0_LATENCY_5_CYCLES 4 -#define L2x0_LATENCY_6_CYCLES 5 -#define L2x0_LATENCY_7_CYCLES 6 -#define L2x0_LATENCY_8_CYCLES 7 - -#define PL310_LATENCIES(Write,Read,Setup) (((Write) << 8) | ((Read) << 4) | (Setup)) -#define PL310_TAG_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup) -#define PL310_DATA_LATENCIES(Write,Read,Setup) PL310_LATENCIES(Write,Read,Setup) - -VOID -L2x0CacheInit ( - IN UINTN L2x0Base, - IN UINT32 L2x0TagLatencies, - IN UINT32 L2x0DataLatencies, - IN UINT32 L2x0AuxValue, - IN UINT32 L2x0AuxMask, - IN BOOLEAN CacheEnabled - ); - -#endif /* L2CACHELIB_H_ */