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[2001:19d0:306:5::1]) by mx.google.com with ESMTPS id u85si12545197pfi.278.2017.12.12.02.38.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:29 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) client-ip=2001:19d0:306:5::1; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=U/iQDIGc; spf=pass (google.com: best guess record for domain of edk2-devel-bounces@lists.01.org designates 2001:19d0:306:5::1 as permitted sender) smtp.mailfrom=edk2-devel-bounces@lists.01.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from [127.0.0.1] (localhost [IPv6:::1]) by ml01.01.org (Postfix) with ESMTP id 482EA220EE10D; Tue, 12 Dec 2017 02:33:49 -0800 (PST) X-Original-To: edk2-devel@lists.01.org Delivered-To: edk2-devel@lists.01.org Received-SPF: Pass (sender SPF authorized) identity=mailfrom; client-ip=2a00:1450:400c:c0c::241; helo=mail-wr0-x241.google.com; envelope-from=ard.biesheuvel@linaro.org; receiver=edk2-devel@lists.01.org Received: from mail-wr0-x241.google.com (mail-wr0-x241.google.com [IPv6:2a00:1450:400c:c0c::241]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 90E5221A1099A for ; Tue, 12 Dec 2017 02:33:47 -0800 (PST) Received: by mail-wr0-x241.google.com with SMTP id v22so20613913wrb.0 for ; Tue, 12 Dec 2017 02:38:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=bTc5NTsvQOhQTmLQ79mDAauv6Ow4Y56JpzkqRRIqdDo=; b=U/iQDIGceXmC2wREJwHCfOLktnkUnSJelpGwpeWgGUKnhIavovtKMHAkt0GcbPbiSl nXPBi2IIzeDPNLeQ8v3NTV5ga+tSIqtXaz75mDqoZ5+UvG6DZVERR3Iac+/dfDwaF3Wv ogUEHhNPVk6YzO4gaR6oxU3K8gIT34BmKGG/4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=bTc5NTsvQOhQTmLQ79mDAauv6Ow4Y56JpzkqRRIqdDo=; b=K0sFXvqU/3eGb+YzCSiW2/g41t9/OoklesWL1dofJnhk7RdcpHvFov1isg7RbiPZTd EjHlnrgPuuNsjgxgBDcBshzbIN1acg6D4zsYeRpf2nsjS3Rx4AmlwcOYqvo6v+Vs11xv 3UxP3xp6S8uN/Xppo5/GkC2opv5qtgJ0MiKAYlbavIJZ0IHIanSu+YxZzADow5BEJY6b VTeZo3vv7G0DFGkIvw0f4qfxhlcAtruUuRzQIcBilWDP5RfVljztxRu4jeSgEykXnRN0 Qesd5tfB+Rqf5ZFS9PpEvwHlRWuUzjTpkz+1v1PY8J+AnKBEMBSKx7RGT63Vdvspv8M0 GivA== X-Gm-Message-State: AKGB3mIY0XGIVj8hJs98DZAQA6mqCtd7ijFIfpiRNi2Qbz3ItHF4CRVz a3D56wrUdRTSHOVjfKJiYm46nse/uq4= X-Received: by 10.223.195.136 with SMTP id p8mr3654182wrf.4.1513075104383; Tue, 12 Dec 2017 02:38:24 -0800 (PST) Received: from localhost.localdomain ([160.171.158.223]) by smtp.gmail.com with ESMTPSA id b16sm21279762wrd.69.2017.12.12.02.38.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 12 Dec 2017 02:38:23 -0800 (PST) From: Ard Biesheuvel To: edk2-devel@lists.01.org Date: Tue, 12 Dec 2017 10:38:03 +0000 Message-Id: <20171212103807.18836-5-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171212103807.18836-1-ard.biesheuvel@linaro.org> References: <20171212103807.18836-1-ard.biesheuvel@linaro.org> Subject: [edk2] [PATCH edk2-platforms 4/8] Silicon/SynQuacerPciHostBridgeLib: enable RCs based on PCD setting X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.thompson@linaro.org, masami.hiramatsu@linaro.org, leif.lindholm@linaro.org, Ard Biesheuvel MIME-Version: 1.0 Errors-To: edk2-devel-bounces@lists.01.org Sender: "edk2-devel" In order to accommodate the EVB, whose PCIe RC #0 should not be touched by software if no card is inserted, add a PCD that tells the PCIe driver code which RCs should be initialized and exposed to the PCI host bridge driver. Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ard Biesheuvel --- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c | 19 ++++++++++--- Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf | 3 ++ Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c | 30 +++++++++----------- Silicon/Socionext/SynQuacer/SynQuacer.dec | 4 +++ 4 files changed, 36 insertions(+), 20 deletions(-) -- 2.11.0 _______________________________________________ edk2-devel mailing list edk2-devel@lists.01.org https://lists.01.org/mailman/listinfo/edk2-devel diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c index 42cdce24b2c4..596862baf469 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.c @@ -92,7 +92,7 @@ CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { #define PCI_ALLOCATION_ATTRIBUTES EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM #endif -STATIC PCI_ROOT_BRIDGE mPciRootBridges[] = { +PCI_ROOT_BRIDGE mPciRootBridges[] = { { 0, // Segment 0, // Supports @@ -149,9 +149,20 @@ PciHostBridgeGetRootBridges ( OUT UINTN *Count ) { - *Count = ARRAY_SIZE (mPciRootBridges); - - return mPciRootBridges; + switch (PcdGet8 (PcdPcieEnableMask)) { + default: + ASSERT (FALSE); + case 0x0: + *Count = 0; + return NULL; + case 0x1: + case 0x2: + *Count = 1; + return &mPciRootBridges[PcdGet8 (PcdPcieEnableMask) - 1]; + case 0x3: + *Count = ARRAY_SIZE (mPciRootBridges); + return mPciRootBridges; + } } /** diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf index 5d87727c73ba..27fcba034418 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLib.inf @@ -49,3 +49,6 @@ [LibraryClasses] [FixedPcd] gArmTokenSpaceGuid.PcdPciIoTranslation + +[Pcd] + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask diff --git a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c index 3da94945f96a..bea40e3dcfe8 100644 --- a/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c +++ b/Silicon/Socionext/SynQuacer/Library/SynQuacerPciHostBridgeLib/SynQuacerPciHostBridgeLibConstructor.c @@ -120,6 +120,8 @@ #define MISC_CONTROL_1_OFF 0x8BC #define DBI_RO_WR_EN BIT0 +extern PCI_ROOT_BRIDGE mPciRootBridges[]; + STATIC VOID ConfigureWindow ( @@ -390,18 +392,12 @@ SynQuacerPciHostBridgeLibConstructor ( IN EFI_SYSTEM_TABLE *SystemTable ) { - PCI_ROOT_BRIDGE *RootBridges; - UINTN Count; UINTN Idx; - RootBridges = PciHostBridgeGetRootBridges (&Count); - ASSERT (Count == ARRAY_SIZE(mBaseAddresses)); - if (Count != ARRAY_SIZE(mBaseAddresses)) { - return EFI_INVALID_PARAMETER; - } - - for (Idx = 0; Idx < Count; Idx++) { - PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { + if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { + PciInitControllerPre (mBaseAddresses[Idx].ExsBase); + } } // @@ -412,12 +408,14 @@ SynQuacerPciHostBridgeLibConstructor ( // gBS->Stall (150 * 1000); - for (Idx = 0; Idx < Count; Idx++) { - PciInitControllerPost (mBaseAddresses[Idx].ExsBase, - mBaseAddresses[Idx].DbiBase, - mBaseAddresses[Idx].ConfigBase, - mBaseAddresses[Idx].IoMemBase, - &RootBridges[Idx]); + for (Idx = 0; Idx < ARRAY_SIZE (mBaseAddresses); Idx++) { + if (PcdGet8 (PcdPcieEnableMask) & (1 << Idx)) { + PciInitControllerPost (mBaseAddresses[Idx].ExsBase, + mBaseAddresses[Idx].DbiBase, + mBaseAddresses[Idx].ConfigBase, + mBaseAddresses[Idx].IoMemBase, + &mPciRootBridges[Idx]); + } } return EFI_SUCCESS; diff --git a/Silicon/Socionext/SynQuacer/SynQuacer.dec b/Silicon/Socionext/SynQuacer/SynQuacer.dec index 02dd6ac417f9..2e18cb33346d 100644 --- a/Silicon/Socionext/SynQuacer/SynQuacer.dec +++ b/Silicon/Socionext/SynQuacer/SynQuacer.dec @@ -38,3 +38,7 @@ [PcdsFixedAtBuild] gSynQuacerTokenSpaceGuid.PcdClearSettingsGpioPin|0xFF|UINT8|0x00000004 gSynQuacerTokenSpaceGuid.PcdI2cReferenceClock|62500000|UINT32|0x00000005 + +[PcdsPatchableInModule, PcdsDynamic] + # Enable both RC #0 and RC #1 by default + gSynQuacerTokenSpaceGuid.PcdPcieEnableMask|0x3|UINT8|0x00000007